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Participant sarman_1998
Participant
793 Views
Registered: ‎05-16-2018

What is a good rule of thumb for output pin slew rate?

For you FPGA experts out there, do you have a rule of thumb you used as a starting point for deciding when to set SLEW to FAST on an output pin?

 

I did some googling and there are many discussions about specific situations but i didn't find any general recommendations and I know i would find that useful.

 

Right now i'm working on a 250 mhz 16 bit parallel interface that goes over an FMC connector.   It seems a good candidate for FAST slew.

 

Thanks,

  Eric

0 Kudos
2 Replies
750 Views
Registered: ‎01-08-2012

Re: What is a good rule of thumb for output pin slew rate?

The rule of thumb that I use is "use the slowest slew rate, the weakest drive strength and the smallest voltage swing that will allow the interface to work with an acceptable bit error rate given the particular PCB / connector / cable technology that I have chosen whilst also meeting the required emission and susceptibility standards".

 

Ultimately, you have to manage trade-offs between all of:

  • Signal integrity (including crosstalk and waveform at the Rx)
  • Timing
  • EMI
  • Ground bounce
  • PCB (and connector) cost

 

In your case, 250MHz probably implies FAST.

717 Views
Registered: ‎06-21-2017

Re: What is a good rule of thumb for output pin slew rate?

In addition to the information that @allanherriman gives, Xilinx FPGAs have a Simultaneously Switching Output (SSO) specification.  Too many outputs switching at once can cause ground bounce or possibly VCCO sagging.  The faster the slew rate and higher the drive, the fewer simultaneously switching outputs you may have on a bank.