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Explorer
Explorer
11,496 Views
Registered: ‎04-29-2010

Xilinx Block/Distributed RAM initialization for synthesis

Hi, 

Can we initialize a block ram or a distributed ram for synthesis using "for" loop?

In my case, I just want to preload all my RAM address locations with the same constant number. What will be the easiest way and the most efficient way of doing this, in Verilog?

 

Thanks, 

--Rudy 

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9 Replies
Xilinx Employee
Xilinx Employee
11,489 Views
Registered: ‎02-14-2014

Re: Xilinx Block/Distributed RAM initialization for synthesis

Hello,

Please check below link
http://www.edaboard.com/thread59213.html

Here you can find discussion on memory initialization using $readmemh and $readmemb system tasks as well as using for loop.
Regards,
Ashish
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Explorer
Explorer
11,478 Views
Registered: ‎04-29-2010

Re: Xilinx Block/Distributed RAM initialization for synthesis

Some of the code examples in the provided ink is actually using "Init" process in Verilog. 

Is Verilog "init" a synthesizable process?!

 

Thanks, 

--Rudy 

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Xilinx Employee
Xilinx Employee
11,453 Views
Registered: ‎02-14-2014

Re: Xilinx Block/Distributed RAM initialization for synthesis

Hello,

'Initial' block in verilog is not synthesizable. It is meant for simulation purpose. But you can use this statement to initialize the memory and check in simulation whether the memory got initialized properly with values in the input file. While reading and writing process you can perform in always block (synchronously if required) which is a synthesizable construct.
Regards,
Ashish
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Teacher muzaffer
Teacher
11,444 Views
Registered: ‎03-31-2012

Re: Xilinx Block/Distributed RAM initialization for synthesis

do it in systemverilog and say:

logic [7:0] foo[512];

initial foo = '{default: 42};
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Explorer
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11,443 Views
Registered: ‎04-29-2010

Re: Xilinx Block/Distributed RAM initialization for synthesis

Thanks for the reply again. But I am still not sure that I understood it properly. Could you please elaborate on it more?

 

1. That was exactly what I was thinking about "init" block. Based on what I read on different websites, it seems that "init" is not synthesizable, just as you mentioned it too. But then here is my question: 

If "init" is not synthesizable, then how can I use it to initialize memory?! If the synthesis tool is going to ignore the "init" block, since it is NOT synthesizable, then how can I put a block of code in there and hope that it will initialize my memory !!!

I completely agree that it will work fine for simulation. But I am not sure how it will work for synthesis !! 

 

 

2. By the way, let's say even if this works, to me it doesn't really look like an initialization. Because it would be running through a for loop to actually load the RAM with some data. 

What I mean is that, let's say that my memory is 2K deep, then right after I bring the chip out of reset, then the code will go through 2K clocks to one by one set my addersses to a desired number. 

 

Where as what I am thinking of a true initialization, is actually initializing the RAM upon coming out of reset, withouht going through a loop to initialize one by one. Can such way or resetting be acheived for a Distributed RAM?

 

 

Thanks, 

--Rudy 

 

 

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Teacher muzaffer
Teacher
11,433 Views
Registered: ‎03-31-2012

Re: Xilinx Block/Distributed RAM initialization for synthesis

It is funny that a Xilinx employee says "initial is not synthesizable". Initial is not synthesizable for ASICs; for FPGAs it definitely is synthesizable. Synthesis tools know how to generate the INIT properties of the block rams from the initial statements in the RTL.

 

Both for block rams and distributed rams, the state after re-programming can be initialized by initial statements and this is supported by synthesis. Of course there is a caveat: this is not doable for a reset but only during re-programming of the FPGA. There is no way to completely clear a block ram during reset; it needs to be written word by word. This is slightly less so for distributed memory. Because they are constructed from smaller individiual pieces, it's much faster to initialize a distributed memory block after reset depending on the aspect ratio.

 

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Xilinx Employee
Xilinx Employee
11,424 Views
Registered: ‎02-14-2014

Re: Xilinx Block/Distributed RAM initialization for synthesis

Hello @muzaffer ,

 

Yes, I agree. 

 

The prior explanation is applicable for ASICs. For FPGA world, initialization is surely taken care by the synthesis tool and init statement can be used for initializing memory. I should have clarified it in my earlier post.

 

Thanks for bringing this point to my notice. 

Regards,
Ashish
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Explorer
Explorer
11,397 Views
Registered: ‎04-29-2010

Re: Xilinx Block/Distributed RAM initialization for synthesis

 

Thanks for clarifying. 

 

Just to fully understand it, then what that means is that let's say if I have a 1024 deep RAM, regadless of whether it is Distribited or Block, then it will take about 1024 clocks to go through one by one of the address locations and initialize the RAMs?

Is the above statement correct?

 

So, that means to make sure that all my address locations have the proper initalized value, then I have to wait about 1024 clocks, before using the RAM! Is this correct?

So there is no other way to initialize a 1024 deep RAM in let's say 1 or 2 clock cycles?

 

 

 

By the way, in the code example that you showed for System Verilog, does initializition have to happen in "init" process?

Can I just do the same thing during the declration?

 

logic [7:0] foo[512] = '{default: 42};

 

Or this will not work?

 

That is also because systemverilog did complain about having two drivers on my memory array (even though I put it in initial block) ... How should I fix this?

 

 

logic [15:0] mem [0:255];

 

initial
  begin
     mem = '{default: 128};
  end

 

// Synchronous Write to RAM

always_ff @ (posedge sys_clkh)
   begin
       if(in_wr_enh)
            mem[in_wr_adh] <= in_dth;
end

 

 

Thanks, 

--Rudy 

 

 

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Teacher muzaffer
Teacher
11,363 Views
Registered: ‎03-31-2012

Re: Xilinx Block/Distributed RAM initialization for synthesis

Block and distributed rams are somewhat different. Distributed rams have much smaller granularity; they come 128 bits at a time. By playing with the aspect ratio of your memories you should be able to initialize them much faster. Block rams on the other hand need to be written 1 word at a time. Even then you can have a wider bram (they can be 72 bits wide) and write at a large stride.
Initialization during declaration should work. I think that avoids multiple writes error. Another option is to use always and use initialize.
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