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Registered: ‎08-23-2011

Xilinx timing summary - setup check and best case for false path meaning?



i applied false path (TIG) constraints in my UCF for the FPGA design. tool is ISE 14.1


TS_fp1 = TIG from 125MHz to 62MHz bus.

TS_fp2 = TIG from 125MHz to 100MHz bus.


However when i implement the design and look at the timing summary, i see messages for the false paths as follows - 

constraint: path "TS_fp1", check:           , best case acvhievable:              , timing score:

constraint: path "TS_fp2" , check: setup, best case achievable: 7.938ns, timing score:0


my question is - 

1) do the blank fields for the TS_fp1 indicate that those paths donot exist in the design (huge design with 1000+ regs/wires so hard to trace all the paths :))?

-if yes, then is it still OK to leave the TS_fp1 in the constraint file or will it mess up the flow/PAR in any way? 


2) for TS_fp2, i see the fields check: setup and best case achievable: 7.938ns, timing score:0.

  1. I know what setup, best case achievable, timing score mean.but what meaning do these fields have for TIG/false paths?
  2. does TIG not mean the tool should not analyse these paths at all? if yes, why are these setup and best case still populated?
  3. also, do i need to do something for these fields or can i simply ignore these messages for TS_fp2?

Do let me know ...


thanks in advance,





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