behavioural simulation works, implementation works, post-synthesis simulation fails---Why?

[davewen]

I'm using Vivado 2015.4 to make a coprocessor on Zynq-7000 with Xillybus. The circuit is mostly complete, and behavioural simulation works (except for this unresolved problem here). After some wrestling with the tools, I managed to convince Vivado to implement the design and generate a bitstream for me.

Then I tried to do a post-synthesis timing simulation and it all goes wrong. For one of the components, the tool keeps telling me, "VRFC 10-718 formal port [port] does not exist in entity [entity]", for basically every single port to the component except, strangely, the synchronous reset signal...!

I've attached the relevant files if you wish to have a look.

I have to say, the advice, "please compare the definition of block to its component declaration to its instantiation" is extremely unhelpful. If this behaviour is expected, surely the least the software can do tell me how to perform a post synthesis simulation properly?

[davewen]

This, by the way, does not solve the problem: at the elaborate step the post synthesis simulation still fails, telling me that ports do not exist and that I should check the declaration and instantiation.