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Visitor jimkey
Visitor
4,625 Views
Registered: ‎04-09-2013

clpd 9500lx

Is switch matrix composed of physical switches, bi-stables that are set on/off thus creating a physical path from input to and/or gate, composed of transistors, etc, or is it all logic or other?

 

Does the processing of logic involve any type of I/O sample and hold or does it react instantly?

 

Is there any delay processing logic after power-up.(Vcc)?

 

Is there any transfer of data to RAM for any purpose? What purpose?

 

 

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4 Replies
Scholar austin
Scholar
4,622 Views
Registered: ‎02-27-2008

Re: clpd 9500lx

Step 1:

 

Google 9500LX CPLD

 

Step 2:

 

Read everything you find

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor jimkey
Visitor
4,606 Views
Registered: ‎04-09-2013

Re: clpd 9500lx

A simple "I don't know" would have sufficed.

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Scholar austin
Scholar
4,595 Views
Registered: ‎02-27-2008

Re: clpd 9500lx

j,

 

You are correct.  I get 'snarky' when I see that people are just too lazy (tired, unmotivated, or just don't) to read what is already out there.

 

I apologize.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Scholar austin
Scholar
4,594 Views
Registered: ‎02-27-2008

Re: clpd 9500lx

"Is switch matrix composed of physical switches,"

 

No.

 

"bi-stables that are set on/off thus creating a physical path from input to and/or gate, composed of transistors, etc,"

 

Yes:  SRAM cells control the logic to create the interconections and the options for the logic (it is called a "programmable logic device").

 

"or is it all logic or other?"

 

Both

 

"Does the processing of logic involve any type of I/O sample and hold or does it react instantly?"

 

That is up to you:  how are you going to design your logic?  Will it sample the data?  Will it pass the data through logic?  That is your choice.  It is called "synchronous logic."

 

"Is there any delay processing logic after power-up.(Vcc)?"

 

Yes, after power up, the programming for all control points is transferred from flash to SRAM (both are internal to the device).  See the data sheet for the power On delay.

 

"Is there any transfer of data to RAM for any purpose? What purpose?"

 

Other than the initialization of the device (flash to SRAM) there is no other RAM.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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