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geco.kevin
Adventurer
Adventurer
5,265 Views
Registered: ‎08-15-2014

csv file based LUT

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Hello all,

 

I am doing a project that requires me to implement a fairly large LUT in verilog. I'd like to generate the values in MATLAB and then import them into the verilog with a .csv or similar file, rather than just typing them all in by hand. Does anyone have any advice as to how to do this?

 

Thanks

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drjohnsmith
Teacher
Teacher
8,951 Views
Registered: ‎07-09-2009

Thank you

 

interesting,

 

Do I understand then by LUT your meaning the RAM blocks,

    and your using them as a Look Up Table to do the distortion ,

 

You can use an external file to load RAMs directly 

    this might give you a few pointers,

 

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Initializing-Block-RAM-with-External-Data-File/td-p/229193

 

Loading RAMS externally is  used a lot in the PicoBlaze project, allows one to change the code in the ram without having to re compile the FPGA completely,

 

Have fun and let us know how it goes,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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evgenis1
Advisor
Advisor
5,223 Views
Registered: ‎12-03-2007

Hi,

 

One way to implement this is as follows. Instead of generating CSV with the LUT values, you can generate Verilog file. Something like that: 

 

initial begin: my_lut_vals

lut_val[0] = 'h11223344
lut_val[1] = 'h55667788
...
end

Then include that file in place you instantiate the LUT.

 

reg [31:0] lut_vals [1:N];
`include "my_lut_vals.vh"

Thanks,

Evgeni

 

 

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drjohnsmith
Teacher
Teacher
5,175 Views
Registered: ‎07-09-2009

Can I ask , for my own knowledge why you want to implement the logic values in MATLAB ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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geco.kevin
Adventurer
Adventurer
5,128 Views
Registered: ‎08-15-2014

I am making a driver, and I want to implement complex digital predistortion to the data. I can use Matlab to generate filters and such and then load the results into a LUT. This takes the burden off of circuitry doing computationally intensive work.

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drjohnsmith
Teacher
Teacher
8,952 Views
Registered: ‎07-09-2009

Thank you

 

interesting,

 

Do I understand then by LUT your meaning the RAM blocks,

    and your using them as a Look Up Table to do the distortion ,

 

You can use an external file to load RAMs directly 

    this might give you a few pointers,

 

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Initializing-Block-RAM-with-External-Data-File/td-p/229193

 

Loading RAMS externally is  used a lot in the PicoBlaze project, allows one to change the code in the ram without having to re compile the FPGA completely,

 

Have fun and let us know how it goes,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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