cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
bowen_fu
Explorer
Explorer
5,293 Views
Registered: ‎04-07-2013

lower DDR4 clock rate on VCU 108 / ultrascale?

 

Hi,

 

In VCU 108 Board, the board differential clock of 300MHz is provided for DDR4 IP core clocks.

eg.

c0_sys_clk_p

c0_sys_clk_n

 

Can I choose other differential clocks: pcie refclk, sysclk_125 ?

or use PLL to generate a lower frequency clock?

 

Thanks!

 

 

0 Kudos
2 Replies
balkris
Xilinx Employee
Xilinx Employee
5,281 Views
Registered: ‎08-01-2008

I would like to know why you want to use alternate clock . Use the same clock as thats tested with MIG design .

You need to generate the MIG again with your new clock constraint .

Follow the guideline and according to that you can make required change.

However i not seeing any benefit to use alternate clock .

check clocking section in MIG product Guide

 

Here is some important document which can help you

http://www.xilinx.com/products/design_resources/mem_corner/ddr4.htm
http://www.xilinx.com/Attachment/Xilinx_Answer_60305_2014_3_.pdf
http://www.xilinx.com/support/answers/60305.html
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0061-ultrascale-memory-interface-ddr4-ddr3-hub.html
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
bowen_fu
Explorer
Explorer
5,253 Views
Registered: ‎04-07-2013

because we are hitting calibration fail a lot. The timing slack of mmcm_clk is bad: -1.7ns.
The utilization is already quite high, like 75%
0 Kudos