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Visitor
Visitor
3,306 Views
Registered: ‎09-07-2009

net delay

Hello

I made a module for multiplexing delay

the problem is when the place & route.
I have a net connect to 32 different point 

I know how to impose the same delay between the point of start and end points

example:
p1 (starting point of the net)
a1 (end point 1 of the net)
a2 (end point 2 of the net)
....
....
a32 (point of arrival 32)


"p1 to a1 = p1 to a2 = ..... = p1 to 32"

thank you in advance
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2 Replies
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Professor
Professor
3,286 Views
Registered: ‎08-14-2007

If it is all one net, you should look at the MAXSKEW constraint in the constraints guide.

 

Something like

 

NET "your_net_name" MAXSKEW = 1 ns;

-- Gabor
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Visitor
Visitor
3,281 Views
Registered: ‎09-07-2009

thank you. but I used 100ps in skew limit, and i see this message

my delay line was a ps delay (200ps of 1mux)

 

--------------------------------------------------------------------------------
Release 11.2 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

D:\xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
D:/Users/Guillaume/FPGA/ISE/V0_1/pulsbox/pulsbox.ise -intstyle ise -v 3 -s 3
-fastpaths -xml mux_chaine_32_bits_preroute.twx mux_chaine_32_bits_map.ncd -o
mux_chaine_32_bits_preroute.twr mux_chaine_32_bits.pcf -ucf
mux_chaine_32_bits.ucf

Design file:              mux_chaine_32_bits_map.ncd
Physical constraint file: mux_chaine_32_bits.pcf
Device,package,speed:     xc5vfx70t,ff1136,-3 (PRODUCTION 1.65 2009-06-01, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
   information.  For accurate numbers, please refer to the post Place and Route
   timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.

================================================================================
Timing constraint: NET "input_nano_delay_IBUF" MAXSKEW = 0.1 ns;
 1 net analyzed, 1 failing net detected.
 1 timing error detected.
 Maximum net skew is   0.486ns.
--------------------------------------------------------------------------------
Slack:     -0.386ns input_nano_delay_IBUF
Report:    0.486ns skew meets   0.100ns timing constraint by -0.386ns
From                         To                           Delay(ns)  Skew(ns)
L4.I                         SLICE_X66Y83.C6               e  0.972  0.448
L4.I                         SLICE_X66Y83.D6               e  0.971  0.447
L4.I                         SLICE_X66Y84.C6               e  0.978  0.454
L4.I                         SLICE_X66Y87.C6               e  0.887  0.363
L4.I                         SLICE_X66Y87.D6               e  0.886  0.362
L4.I                         SLICE_X66Y88.A6               e  0.804  0.280
L4.I                         SLICE_X66Y88.B6               e  0.810  0.286
L4.I                         SLICE_X66Y90.C6               e  0.776  0.252
L4.I                         SLICE_X66Y90.D6               e  0.775  0.251
L4.I                         SLICE_X66Y91.B6               e  0.766  0.242
L4.I                         SLICE_X66Y91.C6               e  0.748  0.224
L4.I                         SLICE_X66Y92.C6               e  0.735  0.211
L4.I                         SLICE_X66Y92.D6               e  0.734  0.210
L4.I                         SLICE_X66Y96.A6               e  0.533  0.009
L4.I                         SLICE_X66Y96.B6               e  0.539  0.015
L4.I                         SLICE_X67Y83.C6               e  0.962  0.438
L4.I                         SLICE_X67Y83.D6               e  0.960  0.436
L4.I                         SLICE_X67Y84.A6               e  1.008  0.484
L4.I                         SLICE_X67Y84.B6               e  1.010  0.486
L4.I                         SLICE_X67Y89.C6               e  0.782  0.258
L4.I                         SLICE_X67Y89.D6               e  0.780  0.256
L4.I                         SLICE_X67Y91.A6               e  0.751  0.227
L4.I                         SLICE_X67Y91.B6               e  0.753  0.229
L4.I                         SLICE_X67Y92.B6               e  0.750  0.226
L4.I                         SLICE_X67Y92.C6               e  0.725  0.201
L4.I                         SLICE_X67Y93.A6               e  0.642  0.118
L4.I                         SLICE_X67Y93.B6               e  0.644  0.120
L4.I                         SLICE_X67Y94.A6               e  0.630  0.106
L4.I                         SLICE_X67Y94.B6               e  0.632  0.108
L4.I                         SLICE_X67Y96.A6               e  0.524  0.000
L4.I                         SLICE_X67Y96.B6               e  0.526  0.002
L4.I                         SLICE_X68Y96.C6               e  0.807  0.283
L4.I                         SLICE_X68Y96.D6               e  0.807  0.283

--------------------------------------------------------------------------------

Message Edited by guillaumekro on 09-07-2009 09:06 AM
Message Edited by guillaumekro on 09-07-2009 09:06 AM
Message Edited by guillaumekro on 09-07-2009 09:07 AM
Message Edited by guillaumekro on 09-07-2009 09:07 AM
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