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Observer alexmiculescu
Observer
3,416 Views
Registered: ‎11-11-2016

parallel vs sequencial

Hi! I don't understand how non blocking assignments are executed in sequence or in parallel?

 

 

always @(posedge clk)
begin
x = 2;
y = x;
end

vs

always @(posedge clk)
fork
x = 2;
y = x;
join

vs

assign x = 2;
assign y
= x;


I don't grasp what is happening at the hardware level. In what cases race condition might occur? If all those are executed in sequence what are the advantages? Thank you!

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2 Replies
Teacher muzaffer
Teacher
3,406 Views
Registered: ‎03-31-2012

Re: parallel vs sequencial

@alexmiculescu minor comment: nonblocking assignments are designated with '<=' also they're only valid in procedural assignments, not continuous.

don't forget that verilog is simulated based on event queues. In a nonblocking assignment, both right hand-sides of the assignment are calculated and put into a queue. When time progresses and the assignments become pending, they are assigned to the left-hand side in the same event step. This allows the parallel execution of nonblocking assignments.

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Scholar u4223374
Scholar
3,325 Views
Registered: ‎04-26-2015

Re: parallel vs sequencial

In hardware it's all parallel. However, the synthesis tool is able to make the parallel hardware act like it's doing sequential execution - so blocking assignments "look" sequential even though they aren't.

Race conditions should not occur. As far as I know, it's not possible to cause a race condition that can actually be synthesized; race conditions tend to result in multiple-driver errors during synthesis. You can get race conditions in hardware (eg. a signal that doesn't quite reach the flip-flop before the relevant clock edge) but those shouldn't occur if the design is correctly constrained and it passes timing. In short, if you're seeing race conditions, the tools will probably be throwing either errors or warnings.

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