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fd31
Visitor
Visitor
7,093 Views
Registered: ‎06-29-2009

problem initialization adc spartan 3an

hello,

I want to configure the A / D converter of my spartan 3AN.
I try to convert values between 1.4 V 1.9 V.
I find the forum a vhdl code (see below) which allows you to initialize the ADC. 
but when I use thise code, it does not works (no signal output).
I identified all the signals from the data sheet, but I did not understand the usefulness of signal SPI_MISO.
this signal is the source of my problem?
someone would have a solution or an another code vhdl for me?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ADC_AMP is

Port ( clk50 : in STD_LOGIC;

ce_amp : in STD_LOGIC;

start_conv : in STD_LOGIC;

SPI_MISO : in std_logic; --adc

CONV : out STD_LOGIC; --adc

ADC1 : out std_logic_vector(13 downto 0) := (others => '0');

ADC2 : out std_logic_vector(13 downto 0) := (others => '0');

gain : in std_logic_vector(7 downto 0);

AMP_CS : out STD_LOGIC;

MOSI : out STD_LOGIC; -- amp

SCK : out STD_LOGIC);

end ADC_AMP;

architecture Behavioral of ADC_AMP is

 

type state_type is (IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD);

signal next_state, state : state_type;

signal counter : integer range 0 to 35 :=0;

signal sample : std_logic;

begin

 

 

process(start_conv,ce_amp,state,counter)

variable bit_count : integer range 0 to 15;

begin

case state is

when IDLE =>

if ce_amp ='1' then

next_state <= START;

else

next_state <= IDLE;

end if;

 

when START =>

next_state <= START2;

bit_count :=0;

when START2 =>

next_state <= HI;

when HI =>

if counter = 2 then

next_state <= HI_DUMMY;

else

next_state <= HI;

end if;

when HI_DUMMY =>

bit_count := bit_count + 1;

next_state <= LO;

when LO =>

if counter = 2 then

next_state <= LO_DUMMY;

else

next_state <= LO;

end if;

when LO_DUMMY =>

if bit_count = 8 then

next_state <= FINE;

else

next_state <= HI;

end if;

when FINE =>

next_state <= IDLE_AD;--inizio a campionare

 

when IDLE_AD =>

if start_conv ='1' then

next_state <= START_AD;

else

next_state <= IDLE_AD;

end if;

when START_AD =>

next_state <= HI_AD;

when HI_AD =>

next_state <= LO_AD;

when LO_AD =>

if counter = 34 then

next_state <= FINE_AD;

else

next_state <= HI_AD;

end if;

when FINE_AD =>

next_state <= IDLE_AD;

when others =>

next_state <= IDLE_AD;

end case;

end process;

process(clk50)

begin

if clk50'event and clk50 ='1' then

state <= next_state;

end if;

end process;

process (clk50)

variable index1 : integer range 0 to 15;

variable index2 : integer range 0 to 15;

begin

if clk50'event and clk50 ='1' then

case state is

when IDLE =>

SCK <= '0';

AMP_CS <= '1';

MOSI <='0';

counter <=0;

when START =>

AMP_CS <= '0';

index1 := 7; -- 8 bit value

when START2 =>

MOSI <= gain(index1); -- ci passo una sola volta dopodichè la assegno in LO_DUMMY

 

when HI =>

 

SCK <= '1';

counter <= counter +1;

when HI_DUMMY =>

counter <=0;

when LO =>

SCK <= '0';

counter <= counter +1;

when LO_DUMMY =>

MOSI <= gain(index1);

index1 := index1-1;

counter <=0;

when FINE =>

AMP_CS <='1';

SCK <= '0';

MOSI <= '0';

when IDLE_AD =>

SCK <= '0';

CONV <= '0';

sample <='0';

when START_AD =>

SCK <= '0';

CONV <= '1';

counter <= 0;

sample <='0';

index1 := 13; -- 14 bit value

index2 := 13; -- 14 bit value

when HI_AD =>

SCK <= '1';

CONV <= '0';

counter <= counter +1;

sample <='0';

when LO_AD =>

SCK <= '0';

CONV <= '0';

 

if(counter >2 and counter < 17) then

-- rappresentazione in complemento a 2

if index1 = 13 then

ADC1(index1) <= not SPI_MISO;

else

ADC1(index1) <= SPI_MISO;

end if;

index1 := index1 -1;

sample <='1';

elsif(counter > 18 and counter < 33) then

-- rappresentazione in complemento a 2

if index2 = 13 then

ADC2(index2) <= not SPI_MISO;

else

ADC2(index2) <= SPI_MISO;

end if;

index2 := index2 -1;

sample <='1';

else

sample <='0';

end if;

when FINE_AD =>

counter <= 0;

sample <='0';

SCK <= '0';

CONV <= '0';

when others =>

SCK <= '0';

CONV <= '0';

AMP_CS <= '1';

MOSI <='0';

end case;

end if;

end process;

 

 

end Behavioral;

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6 Replies
fd31
Visitor
Visitor
7,081 Views
Registered: ‎06-29-2009

thank you in advance !

 

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eilert
Teacher
Teacher
7,065 Views
Registered: ‎08-14-2007

Hi,

the SPI_MISO Signal is quite useful, if not one of the most important signals in your Design.

 

It's the data input to the FPGA of your SPI Interface (Master In Slave Out).

Once your ADC is configured it schould send data over that line.

Either automatically or on request, depending on the configuration.

 

Do you have an UCF file that connects the signals of your design to the right pins?

 

Have a nice synthesis

  Eilert

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fd31
Visitor
Visitor
7,065 Views
Registered: ‎06-29-2009

thank you for your replie.

 

yes I have a UCF file, but I don't know on which FPGA pin I must assign the SPI_MISO signal.

it's not specified in the datasheet.

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eilert
Teacher
Teacher
7,049 Views
Registered: ‎08-14-2007

Hi,

look at the schematic of your board. There you can see, how the ADC is connnected to the FPGA.

 

If you are using a Xilinx Starter Kit a UCF file can be found in the documentation.

Are you using that one? If so make sure, that the signal names in the UCF file and in your sourcecode are the same.

 

Have a nice synthesis

  eilert

 

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fd31
Visitor
Visitor
7,046 Views
Registered: ‎06-29-2009

hi,

Yes I use a Xilinx Starter Kit and I use the UCF file to the documentation.

In this UCF file, there are a signal SPI_MOSI (output of the FPGA), but there isn't signal SPI_MISO.

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abbas_0612000
Visitor
Visitor
5,156 Views
Registered: ‎02-09-2011

NET "AD_CONV" LOC = "Y6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "AD_DOUT" LOC = "D16" | IOSTANDARD = LVCMOS33 ;

 

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