reg: DCM DRP and re configuring the DCM freq during runtime ...
i was using the xilinx V5 XC5VSX50T board and i had to change the DCM freq on the fly. i looked up online and the documentation said that we can use a drp module (dynamic reconfiguration port) to change the multiply/divide values of the DCM.
i wanted to know if this DRP module is an IP core or a xilinx primitive? how can i instantiate it in my design? Do i have to add it via the IP wizard or some other way to incorporate it into my desgin? and is the DCM DRP the same as PLL?