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Explorer
Explorer
7,814 Views
Registered: ‎08-23-2011

reg: ucf file constraints ...

hi, 

i had some questions reg some ucf constraints. 

 

if i interface an fpga device (say xc5vsx50t) with some external device (like a zbt sram), then how can i decide if the UCF constraint slew should FAST or SLOW for an o/p pin? is there any particular value, feature, rate, etc. that I can look for in the datasheet of the external device that can tell me if slew should be FAST or SLOW? the sram works from 160 to 200MHz.

 

also, the zbt sram i have has operating voltage of 2.5 to 3.3v. so in this case, as per the levels, i can use the iostandard of lvttl or lvcmos25 ... so can i use either or is there some restriction on when to use which iostandard?

 

lastly, how can i decide what the drive strength of the o/p pin should be? this drive strength should correlate to which value of the external device so that the current matches and the device can work properly?

 

Do let me know if there are any particular rules to decipher which constraint goes where and gets what value ...?

 

Thanks and regards,

Z

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7 Replies
Mentor hgleamon1
Mentor
7,798 Views
Registered: ‎11-14-2011

Re: reg: ucf file constraints ...

Before I answer this I will qualify myself by saying that what follows shouldn't be taken as gospel :)

 

SLEW RATE

Choosing the slew rate for your signal will be largely dependent on what frequency your data is being transmitted at. You don't want the rise/fall time of the data to be in the same order of magnitude as the data period. Does the ZBT RAM datasheet indicate what slew rate it has (or expects) on its data? You should aim to match it. HOWEVER - having too many FAST slew rate pins in one bank may lead to SSO (simultaneous switching output) noise issues in the device, You should check the FPGA datasheet for allowable maximums.

 

IOSTANDARD

Again, in general, this is dependent on what you are interfacing to. If you are transmitting/receiving data from an LVTTL source, you should match it. I would have expected a RAM to be LVCMOS but then perhaps the RAM datasheet will tell you more.

 

DRIVE STRENGTH

Drive Strength will be dependent on the line impedance of your data. If you are driving a signal across the board or trying to source illuminate an LED, you may need to up the strength. If you have very short tracks, like a parallel connection to a RAM could be, you may not need such high strength. The higher the drive strength, the more overshoot and ringing you may find on your signal. My experience with this is that it is experience-based. However you calculate it, you'll need to verify it on the board anyway so take your best guess, measure it and change it if necessary. Also note that SSO noise (as mentioned above) can be affected by too many high strength outputs. Again, check the FPGA datasheet for allowable maximums.

 

Hope this helps (or helps someone more knowledgeable than me correct my mistakes!).

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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Instructor
Instructor
7,793 Views
Registered: ‎08-14-2007

Re: reg: ucf file constraints ...

I'd just like to add that slew rate, drive stength, and IO standard all affect the interface timing.  The

device data sheet has a table of delay "adders" for each IO standard, drive strength, slew rate

combination.  These will give you an idea of how each parameter affects timing.

 

Simultaneous switching issues are more pronounced with faster slew rate, higher interface voltages,

and higher drive strength.  Luckily Virtex 5 parts are packaged such that even at the fastest edge

rates the SSO issues are minimised.  This may not be the case in cheaper devices which are typically

in packages with more lead inductance.

 

If you're using a source-synchronous interface (FPGA drives clock and data to the RAM), then keeping

the settings the same for all outputs will keep the skew at a minimum, and you may be able to use

slower slew rates or lower drive strength because of the matching "adder" delays.  Usually in a

memory interface, it's the return (read data) data path where you run into problems with high-speed

sampling.  This is much more likely to determine the required output speed of the interface, because

now the delays are additive.  Again you may be able to use a slower output speed if your logic has

a dynamic sampling point adjustment like the MIG core, which calibrates out the external round

trip delays.

 

-- Gabor

-- Gabor
Explorer
Explorer
7,786 Views
Registered: ‎08-23-2011

Re: reg: ucf file constraints ...

hi hgleamon1, 

 

thanks for your reply. 

 

for iostandard and drive strenght, i can understand that it is experience based and can vary. i.e if the voltage level of the peripheral device is from 2.5v to 3.3v, we can use either lvcom or lvttl. and so on for the drive strength too, depending on trace length, impedence etc.

 

however, i am more concerned about slew rate. as i mentioned in my original post, the only factors i've seen in the peripheral device datasheet are rise/fall time - around 1 - 2 ns and setup and hold times - around 5 ns. and the device itself works at 200MHz (max). so would this need a FAST slew rate or a SLOW slew rate? (i guess fast)

 

upto what rise time/fall time, should i take the slew rate to be slow and above that, a slew rate of fast? will it depend on riste/fall time or setup/hold time or some other factor? 

 

as such, in the datasheet i have, there is nothing special that specifies the device slew rate as such ... 

 

do let me know ... thanks for any other inputs ...

 

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Mentor hgleamon1
Mentor
7,779 Views
Registered: ‎11-14-2011

Re: reg: ucf file constraints ...

First up:

 

DS202 is the DC and switching characteristics for Virtex 5. Choose your IOSTANDARD and then look through the tables on, for example, page 32 for details of SLOW and FAST slews for your devices speed grade. Think about what I and Gabor wrote and apply your best judgement.

 

On an additional note:

If the RAM is powered by a given voltage (let's say 3.3V), I suggest that you power your RAM interface by the same voltage. If the RAM can handle LVTTL, then that could be a suitable IOSTANDARD. If the RAM only accepts LVCMOS, then you should probably pick that IOSTANDARD. How could you select an IOSTANDARD otherwise?

 

Also note that, once you have picked an IOSTANDARD for a bank, EVERY pin of that bank must be the same IOSTANDARD.

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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Historian
Historian
7,773 Views
Registered: ‎02-25-2008

Re: reg: ucf file constraints ...


@hgleamon1 wrote:

 

Also note that, once you have picked an IOSTANDARD for a bank, EVERY pin of that bank must be the same IOSTANDARD. 


Clarification: every pin in a bank must have a voltage-compatible IOSTANDARD. So it is perfectly fine for LVDS_25 and LVCMOS25 pins to share the same bank, because they have the same bank supply voltage.

 

----------------------------Yes, I do this for a living.
Mentor hgleamon1
Mentor
7,771 Views
Registered: ‎11-14-2011

Re: reg: ucf file constraints ...


@bassman59 wrote:

@hgleamon1 wrote:

 

Also note that, once you have picked an IOSTANDARD for a bank, EVERY pin of that bank must be the same IOSTANDARD. 


Clarification: every pin in a bank must have a voltage-compatible IOSTANDARD. So it is perfectly fine for LVDS_25 and LVCMOS25 pins to share the same bank, because they have the same bank supply voltage.

 


Ah, yes. Thanks for that. Good spot.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Instructor
Instructor
7,762 Views
Registered: ‎08-14-2007

Re: reg: ucf file constraints ...

Regarding the choice of LVTTL or LVCMOS, there is no real difference for FPGA outputs, LVTTL outputs

drive to the rails just like LVCMOS.  The main difference is in the input voltage thresholds, which in

the case of LVTTL are not relative to Vcco, and can be quite asymmetric as the bank voltage gets lower.

For a high-speed interface, the slew-time can be a significant portion of the clock to output delay,

and you need to be careful that the input logic threshold doesn't add too much additional time

as in the case of LVTTL with 2.5V Vcco, where the high logic threshold becomes close to the

positive rail.  I would suggest reading the fine data sheet from the memory chip, and see what the

test conditions are when they report output timing.  Most likely they will have a diagram that

shows the threshold levels used for the reported timing values.

 

-- Gabor

-- Gabor
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