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Observer
Observer
5,615 Views
Registered: ‎11-23-2010

setting hold time using offset out ...

Hi,

 

I have a question reg. setting the hold time for FPGAs.

 

I have a design that does fine in bhv sim and post PAR sim. all the timing constraints etc. are met. Design runs at 40MHz.

 

Now in the timing report, I see that the min allowable offset out time is 4.2 ns and currently my UCF file has the constraint of  OFFSET = OUT 5 ns AFTER CLK; so this works fine. But in the post PAR sims, I still see a delay between the rising edge of the clk and the o/p signal as 4.2 ns and not 5 ns.

 

I was told that in post PAR sims, the constraints are not taken, but only the delay values calculated in PAR, hence I dont see a 5ns delay. Is my understanding correct?

 

Also, suppose I want to give my o/p signal to a chip that has a hold time of ... say 6 ns, and uses the same clk as that of the FPGA. So now, if I give the o/p signal directly, then since the offset out constraint is 5 ns, it might lead to a metastability issue. So will it be enough to increase the offset out to ... say 7 ns in the UCF file?

 

since I dont see the offset out constraint take effect in post PAR sims, I am just a bit concerned that if I do specify an offset out constraint, it does take effect on the o/p pin, after the specifed delay.

 

Please confirm/let me know ...

 

Thanks,

Z.

 

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Teacher
Teacher
5,608 Views
Registered: ‎11-14-2011

Re: setting hold time using offset out ...

To the best of my knowledge, setting the OFFSET OUT constraint merely defines a limit of what you consider to be acceptable. It does not force the tools to MEET that EXACT timing.

 

So if you specify an OFFET OUT of 6 ns, the tools will do their best to PAR to be inside that limit, not meet it exactly. Subsequently, increasing your OFFSET OUT constraint may not affect anything at all, in terms of actual hardware (although if it is relaxed, then the placer may not have to work so hard to meet the limiting constraint).

 

If you wish to purposefully ADD a delay to an output signal,I think you should concentrate on the IODELAY element.

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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Observer
Observer
5,605 Views
Registered: ‎11-23-2010

Re: setting hold time using offset out ...

Hi,

 

Thanks for your reply. So, I guess this is what you're saying -

 

if the PAR can do a min offset out delay of 4.2 ns, then IT WILL do that delay and not go for a 6 or 7 ns delay, which one might specify in the UCF file.

 

So the UCF offset out constraint only specifies the min. offset delay. But if the tool can do better (lesser) than that, it will ... and will keep that delay, irrespective of the value in the UCF file.

 

Please let me know if my understanding is correct, and if so, then does it not demolish the purpose for OFFSET OUT?

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Teacher
Teacher
5,595 Views
Registered: ‎11-14-2011

Re: setting hold time using offset out ...

So the UCF offset out constraint only specifies the min. offset delay

No, it sets the MAXIMUM ALLOWABLE OFFSET OUT for your design.

 

demolish the purpose for OFFSET OUT

Understand the difference between a CONSTRAINT and a SPECIFICATION. These constraints are setting boundaries for your design.

 

Regards,

 

Howard

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"That which we must learn to do, we learn by doing." - Aristotle
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