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Explorer
Explorer
10,274 Views
Registered: ‎08-23-2011

some questions regarding ISE 14.1 SmartXplorer ...

hi,

 

i have this BIG design which i have implemented on the fpga (a virtex 6 device). 

 

one of the clocks of the design (clk xyz) needs to run @ 125MHz.  however implementing the design only gives about 88MHz. I have constrained the design the best I can (with whatever info I had regarding false paths etc.).

 

so i used SmartXplorer and ran it in the following manner -

1) timing improvement strategy - 12 runs - this would iterate through the various MAP options for best performance

-this gave a best case of 97MHz for clock xyz (using the MapLogicOpt strategy)

2) iterate only on cost table - 12 runs - to try different PAR.

-this gave a best case of 104MHz for clock xyz

 

Now when I tried the bit files on the FPGA, the 104MHz bit file did not work as expected. However the 97MHz bit file did work.

 

My question is - could this be a "fluke" i.e. a slower bit file is working but not the one with a slighlty better timing?

what could be the reasons behind it and where can i look to zero in on it? any files that i can compare between the two runs?

 

will running smartxplorer with more iterations on the cost table help improve the timing of clk xys?

 

If I want  to retian the PAR from the best smartxplorer run for some other implementation run, what is the best way to do that?

 for now, i use planahead and lock the BRAM instances (xilinx document says lock primitives like DSP, BRAMS, arith units etc.), which gives me new loc constraints in the ucf file. I then use these constraints in other xilinx implementation runs to try and retain the PAR to some extent. is this the way to retain PAR or is there some better method to do so?

 

any other things I can try with smartxplorer to improve timing and make the bit file more relaible?

 

all of the above in xilinx 14.1 ISE.

 

 

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7 Replies
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Xilinx Employee
Xilinx Employee
10,265 Views
Registered: ‎07-31-2012

Hi,

 

You seem to have done the right things for closing the timing for best possible frequency. 

 

read through Pg 142 on selecting the best strategy for smartxplorer- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/devref.pdf

 

 

Skim through these guide and see if you can find something new.

 

http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_using_smart_xplorer.htm

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug689.pdf

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
10,261 Views
Registered: ‎07-31-2012

Hi,

 

In any case, you may also have to manually have a look at the code to see if there are some simple paths which can be ingnored for timing or if you can change the coding so that certain registers in the data path can be removed which can improve the timing or something simiilar

Thanks,
Anirudh

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Explorer
Explorer
10,256 Views
Registered: ‎08-23-2011

anirudh,

 

i've already skimmed through these docs and i have read them. that is what got me this far.

 

what i need to know is - what factors could lead to a slower bit file or a bit file from the 2nd best strategy performing better than a bitfile from a better strategy or bitfile which gives a lowe slack on the same clock bus, like the questions i asked

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Explorer
Explorer
10,255 Views
Registered: ‎08-23-2011

hi,

 

i cant change the code as it's an IP. so i have to rely on tools/smartxplorer for the best possible timining. as for looking at the code and manually and figuring out various false paths etc., that information resides with designer .. and it's an IP. so we can't say for sure which path can be ignored or not.

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Highlighted
Explorer
Explorer
10,253 Views
Registered: ‎08-23-2011

My question is - could this be a "fluke" i.e. a slower bit file is working but not the one with a slighlty better timing?

what could be the reasons behind it and where can i look to zero in on it? any files that i can compare between the two runs?

 

will running smartxplorer with more iterations on the cost table help improve the timing of clk xys?

 

If I want  to retian the PAR from the best smartxplorer run for some other implementation run, what is the best way to do that?

 for now, i use planahead and lock the BRAM instances (xilinx document says lock primitives like DSP, BRAMS, arith units etc.), which gives me new loc constraints in the ucf file. I then use these constraints in other xilinx implementation runs to try and retain the PAR to some extent. is this the way to retain PAR or is there some better method to do so?

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Xilinx Employee
Xilinx Employee
10,237 Views
Registered: ‎04-16-2012

Hello @zubin_kumar31

 

I suggest you to run unconstrained timing analysis on the design and check for timing issues.

 

Thanks,

Vinay

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Explorer
Explorer
10,231 Views
Registered: ‎08-23-2011

hi vinay.

 

this is something i am yet to explore. 2 questions regarding your approach -

 

1) if i run an unconstrained analysis on the design, then how will the tool even identify timing issues because ... well ... the design is unconstrained ... so it won't have any violating paths etc. to report.

 

2) when i constraint the design, i get a proper design summary with the failing paths and the best achievable clk frequency. however if i remove the period constraints and then implement the design, then which file do i need to look into to check the best doable frequency for the various clocks/clock domains? 

 

please let me know ...

 

thanks and regards,

z.

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