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Anonymous
Not applicable
4,362 Views

stuck for the clock

Hello all,

 

I am fairly new to the FPGA world, at the moment I need to drive a DAC circuit from a FPGA board,

but Im stuck because I cannot correctly control the clock (200MHz):

 

I recently  learnt how to generate that frequency from a 100MHz clock (the system clock) by using a DCM,

then I checked the result with an oscilloscope and the frequency is correct but it is sine wave (instead of square)

with a high dc offset (around 1v) and a small amplitude (0.2V pk-pk ) when that port is supposed to give 0-3.3V.

I also tried with lower frequencies and I observed similar results but less dramatic. 

 

I would like to know if this is somewhat normal and if it can be solved via software

(I wouldnt like to make an extra analog circuit, if it is not necesssary)

 

PS: does anybody has a good reference to understand the differences beetwen bufg and ibufg?

 

Cheers. 

 

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3 Replies
jprovidenza
Voyager
Voyager
4,355 Views
Registered: ‎08-30-2007

Driving 200 MHz onto a 3.3V pin will give you long term grief.  This is a pretty high

frequency and you better be very careful about signal termination, ie, impedance control.

 

If you don't know what this is, do some studying - you're going to need to understand this

at the 200 MHz rates!

 

Do you have the SLEW=FAST option set for your clock pin in your constraints for the

clock output pin?

 

Is your clock output pin terminated at the end of the signal line?  Or are you using series

termination?  Have you thought about this?

 

At 200 MHz, have you thought about how you provide the proper data setup/hold time for

the DAC data?

 

 

You can look at other threads for BUFG vs IBUFG, but basically both are clock buffers, but

one of them is for input pins, the other routes an internal signal to a global clock line.

 

Good luck!

 

John Providenza

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bassman59
Historian
Historian
4,346 Views
Registered: ‎02-25-2008


z10n0101 wrote:

Hello all,

 

I am fairly new to the FPGA world, at the moment I need to drive a DAC circuit from a FPGA board,

but Im stuck because I cannot correctly control the clock (200MHz):

 

I recently  learnt how to generate that frequency from a 100MHz clock (the system clock) by using a DCM,

then I checked the result with an oscilloscope and the frequency is correct but it is sine wave (instead of square)

with a high dc offset (around 1v) and a small amplitude (0.2V pk-pk ) when that port is supposed to give 0-3.3V.

I also tried with lower frequencies and I observed similar results but less dramatic. 

 


What is your 'scope's analog bandwidth?

 

What is your probe's analog bandwidth?

 

To what point are you connecting the 'scope probe ground? (Hint: the 3"-long ground wire will induce errors!)

 


 

I would like to know if this is somewhat normal and if it can be solved via software

(I wouldnt like to make an extra analog circuit, if it is not necesssary)

 


 It's probably a measurement artifact. See above.

 


 

PS: does anybody has a good reference to understand the differences beetwen bufg and ibufg?

 

Cheers. 

 


 

The data sheets and family user guides have perfectly excellent explanations. I invite you to read them.

 

-a

----------------------------Yes, I do this for a living.
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shantanu75
Explorer
Explorer
4,344 Views
Registered: ‎04-06-2009

John has pointed out some basic andd good points, which one has to always check while playing with high speed CLK.

When ever you are connecting a Clk to a CLK pin of the FPGA - you shld connect a IBUFG after the Clk Pin. Its a part of IOB.

 

Regarding your problem with CRO - I'll like to bring one a very basic point, which many times a designer from software background miss. The sampling freq of the CRO also plays a big role for displaying a waveform. Say if one is using 100MHz CRO to check 50MHz Square wave, he will get a triangular waveform in the screen. Similarly if you are using a 500MHz CRO for 200MHz Square wave, you will get a sine wave like waveform in the screen. Also the capacitance of the Probe plays a big role.

 

You should make confirm the time period is what you expect. And the overshoot and Undershoot should be within limits. If it is you can connect the device - atleast it will not damage your device.

 

 

BUFG is required to increase the fan out. Say you should connect the Bufg to the output of DCM and then should take the clk o/p from the o/p of bufg for your design. For details check out the following links -

 

http://www.xilinx.com/itp/xilinx8/books/data/docs/lib/lib0061_25.html

http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0230_198.html

 

Shantanu

 

 

 

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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