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Participant amki
Participant
2,800 Views
Registered: ‎08-29-2017

synthesis a part of fpga in vivado

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hi 

i have a project that is a big algorithm . and i have to change  a few time a part of  this algorithm  

i want to synthesis just apart of algorithm that changed.

can any one help me out to this issue?

thanks a lot

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Xilinx Employee
Xilinx Employee
4,831 Views
Registered: ‎09-20-2012

Re: synthesis a part of fpga in vivado

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Hi @amki

 

If you have separate RTL file for this module which you modify, you can enable OOC synthesis on that module. This way when you do any change in this module you will need to rerun only the OOC synthesis run, the remaining RTL is not synthesized again. 

 

Refer to "Setting a Bottom-Up Out-of-Context Flow" section in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
4,832 Views
Registered: ‎09-20-2012

Re: synthesis a part of fpga in vivado

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Hi @amki

 

If you have separate RTL file for this module which you modify, you can enable OOC synthesis on that module. This way when you do any change in this module you will need to rerun only the OOC synthesis run, the remaining RTL is not synthesized again. 

 

Refer to "Setting a Bottom-Up Out-of-Context Flow" section in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Moderator
Moderator
2,769 Views
Registered: ‎11-09-2015

Re: synthesis a part of fpga in vivado

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Hi @amki,

 

If the change you want to do is on a part of an active design (on the FPGA), it is called Partial Reconfiguration. See UG909

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant amki
Participant
2,762 Views
Registered: ‎08-29-2017

Re: synthesis a part of fpga in vivado

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thanks for your reply

What should i do for place and route for a part seperate of algorithm in vivado?

thanks alot

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Moderator
Moderator
2,749 Views
Registered: ‎11-09-2015

Re: synthesis a part of fpga in vivado

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Hi @amki,

 

It would be partial reconfiguration.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant amki
Participant
2,739 Views
Registered: ‎08-29-2017

Re: synthesis a part of fpga in vivado

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thanks alot for reply

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Participant amki
Participant
2,719 Views
Registered: ‎08-29-2017

Re: synthesis a part of fpga in vivado

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hi

i read user guide 909 and in Partial Reconfiguration in tools  my vivado have not this option in my tools with i have valid Partial Reconfiguration license.

thanks for your help

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Xilinx Employee
Xilinx Employee
2,716 Views
Registered: ‎09-20-2012

Re: synthesis a part of fpga in vivado

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Hi @amki

 

The version of vivado you are using is old, in 2016.2 PR is supported only in non project mode.

 

Also if you are looking at implementing submodules separately and reuse the results in top level implementation, check the reuse flows in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug905-vivado-hierarchical-design.pdf

Thanks,
Deepika.
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Participant amki
Participant
2,690 Views
Registered: ‎08-29-2017

Re: synthesis a part of fpga in vivado

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thanks alot  for reply

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