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Explorer
Explorer
5,280 Views
Registered: ‎08-23-2011

timing score = 0, all constraints met, but .twx report shows some failing paths ...

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hi,

 

im using xilinx 14.1 for some design implementation. design is implemented properly - translate, map, par all pass.

reports are clean.

par report has no timing error. design summary shows all constraints met and timing score = 0. 

 

but the .twx report has some failing paths with setup/hold issues.

 

eg (hold path) - 

Slack (hold path): -0.012ns (requirement - (clock path skew + uncertainty - data path))
Source: top/bm_top/i2c_bm_wdata_d[0] (FF)
Destination: top/vou_top/vou_vf0/vf1_gm_G/lv_gamma_ram/ram_ram_0_0 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.383ns (Levels of Logic = 0)
Clock Path Skew: 0.181ns (1.588 - 1.407)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.214ns

 

eg (setup path) -

Slack (setup path): -0.228ns (requirement - (data path - clock path skew + uncertainty))
Source: top/bky_reg/r_vsc_h_num[4] (FF)
Destination: top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/gpix_dp/rsum0[12] (FF)
Requirement: 10.000ns
Data Path Delay: 9.962ns (Levels of Logic = 4)
Clock Path Skew: -0.052ns (3.230 - 3.282)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 10.000ns
Clock Uncertainty: 0.214ns

 

NOTE - in the above source/destination paths, for setup and hold, clock domain crossing is happening.

 

Questions - 

 

 

1) so i wanted to know that if the timing score = 0 and the design is implemented and no timing errors show up in PAR report, then should we still bother about the above failing constraints in the .twx report?

 

2) in another thread, i read that such hold path violations, if a CDC is happening, then it can be overlooked. is that correct?

 

3) Would the same apply for setup violations?

 

4) Is the design considered fine and "properly implemented" if the timing score is 0 and map/PAR pass without errors even though we have the above sort of timing messages in the .twx report?

 

please let me know ...

 

z.

 

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1 Solution

Accepted Solutions
Explorer
Explorer
8,784 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

Jump to solution

update - just in case someone runs into the same issue ...

 

my device speed grade was -3 and when i implemented the design, the timing score was 0.

 

however in the post PAR static timing report, the speed grade for the report was set to -1 ... so that gave errors in the .twx report. 

 

that difference kinda threw me off ...

 

hope this helps ...

 

z.

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1 Reply
Explorer
Explorer
8,785 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

Jump to solution

update - just in case someone runs into the same issue ...

 

my device speed grade was -3 and when i implemented the design, the timing score was 0.

 

however in the post PAR static timing report, the speed grade for the report was set to -1 ... so that gave errors in the .twx report. 

 

that difference kinda threw me off ...

 

hope this helps ...

 

z.

0 Kudos