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17134
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PCIe and CPM
Discuss topics on PCI Express, XDMA and QDMA, and the Versal CPM block.
Latest Topic - Versal ACAP VMK180 Targeted Reference Design PCIe ...
| 17134 Posts | 04-19-2021 04:02 AM | |
20080
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Ethernet
Discuss Topics on Xilinx FPGA and ARM Processor System Ethernet IP, High
Speed Channelized Cryptography Engine(HSC), and associated SW stack.
Latest Topic - VMK180 does not link to nVidia (Mellanox) MCX415A-...
| 20080 Posts | 04-19-2021 06:55 AM | |
28469
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Video and Audio
Discuss Video Processing and Connectivity IP – HDMI, DisplayPort, UHD-SDI, Video Processing Subsystem, VCU, and more.
Latest Topic - VCU118 pass-through design sink connection difficu...
| 28469 Posts | 04-19-2021 08:19 AM | |
9606
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Serial Transceivers
Discuss transceiver and transceiver wizard related topics.
Latest Topic - how to verify placement of GT ?
| 9606 Posts | 04-19-2021 08:24 AM | |
18234
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Memory Interfaces and NoC
Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII, LPDDR2 and LPDDR3, MCB, HBM Controller, and related topics.
Latest Topic - app_rd_data strange behavior
| 18234 Posts | 04-19-2021 02:18 AM | |
12572
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AI Engine, DSP IP and Tools
Discuss AI Engine, System Generator, Model Composer, and Digital Signal Processing Ips such as Modulations, Filters, Transforms, Wireless (DPD, PC-CFR), Error Correction, and more.
Latest Topic - VCK190
| 12572 Posts | 04-19-2021 08:15 AM | |
52523
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Processor System Design and AXI
Discuss Processor System design for Versal, Zynq UltraScale+, Zynq-7000, and MicroBlaze.
PS and PL peripherals covered Interrupts, Timers, GPIO, UART, PS-SPI, USB, SATA, I2C, UART, CAN, CAN-FD, RTC, and EPC. Versal Control, Interface & Processing System (CIPS) Wizard and Processor Configuration Wizard (PCW). AXI infrastructure IPs such as AXI-stream, interconnect, memory-mapped.
Latest Topic - Parameter propagation AXI4Stream
| 52523 Posts | 04-19-2021 06:26 AM | |
9975
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Versal and UltraScale Architecture™
A board to discuss topics on Versal, Kintex UltraScale, Virtex UltraScale, Kintex UltraScale+, Virtex UltraScale+, Zynq UltraScale+ MPSoC, and Zynq UltraScale+ RFSoC including Device Architecture, Clocking, SelectIO, Signal Integrity, Packaging, Power, Data Converters and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the other forums.
Latest Topic - RFDC reference clock in zcu111
| 9975 Posts | 04-19-2021 07:37 AM | |
5636
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ACAP and SoC Boot and Configuration
Discuss board bring-up, boot and configuration topics for Versal, Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze based FPGA designs. Topics include secure and non-secure boot flow including programming the boot device (QSPI, JTAG, SD eMMC, NAND, NOR), bootrom, FSBL, loading of the bitstream, fallback/multi-boot, programming of eFUSEs and BBRAM.
Latest Topic - Unable to boot from qspi and able to boot from Mic...
| 5636 Posts | 04-19-2021 03:54 AM | |
32791
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Other FPGA Architecture
A board to discuss topics on Artix™-7, Kintex™-7, Spartan™-7, Virtex®-7, Virtex® Family FPGAs and Spartan® Family FPGAs including Zynq-7000 SoCs including device architecture, clocking, SelectIO, signal integrity, packaging, power, and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the Embedded forums.
Latest Topic - Legacy Node-locked IP License Use
| 32791 Posts | 04-19-2021 07:29 AM | |
18034
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FPGA Configuration
Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, SEM IP, Programming cables, Tandem, iMPACT, and Vivado Device Programmer software related topics. Boot for Versal, Zynq Ultrascale+ and Zynq-7000 is not covered here.
Latest Topic - [SEM IP] Problem with voltage levels after adding ...
| 18034 Posts | 04-19-2021 08:21 AM | |
25299
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Xilinx Evaluation Boards
Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs.
Latest Topic - VCK190
| 25299 Posts | 04-19-2021 06:38 AM | |
13944
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Vivado Debug and Power Estimation Tools
Discuss IP and tools including Chipscope, Integrated Logic Analyzer (ILA), IBERT, VIO, XPE and Power Estimation tools, and others.
Latest Topic - Me podrian ayudar a intalar vivado 2020.1 me apare...
| 13944 Posts | 04-19-2021 07:48 AM | |
7794
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Xilinx IP Catalog
Discuss Topics on all Xilinx IP not included on other boards like BRAM/FIFO, Distributed Logic Generator, ECC, Xilinx Parameterized Macro (XPMs) , CPRI and JESD.
Latest Topic - Parameter propagation AXI4Stream
| 7794 Posts | 04-19-2021 12:40 AM |
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