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Discuss topics on PCI Express, XDMA and QDMA, and the Versal CPM block.
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Discuss Topics on Xilinx FPGA and ARM Processor System Ethernet IP, High
Speed Channelized Cryptography Engine(HSC), and associated SW stack.
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Discuss Video Processing and Connectivity IP – HDMI, DisplayPort, UHD-SDI, Video Processing Subsystem, VCU, and more.
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Discuss transceiver and transceiver wizard related topics.
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Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII, LPDDR2 and LPDDR3, MCB, HBM Controller, and related topics.
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Discuss AI Engine, System Generator, Model Composer, and Digital Signal Processing Ips such as Modulations, Filters, Transforms, Wireless (DPD, PC-CFR), Error Correction, and more.
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Discuss Processor System design for Versal, Zynq UltraScale+, Zynq-7000, and MicroBlaze.
PS and PL peripherals covered Interrupts, Timers, GPIO, UART, PS-SPI, USB, SATA, I2C, UART, CAN, CAN-FD, RTC, and EPC. Versal Control, Interface & Processing System (CIPS) Wizard and Processor Configuration Wizard (PCW). AXI infrastructure IPs such as AXI-stream, interconnect, memory-mapped.
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A board to discuss topics on Versal, Kintex UltraScale, Virtex UltraScale, Kintex UltraScale+, Virtex UltraScale+, Zynq UltraScale+ MPSoC, and Zynq UltraScale+ RFSoC including Device Architecture, Clocking, SelectIO, Signal Integrity, Packaging, Power, Data Converters and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the other forums.
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Discuss board bring-up, boot and configuration topics for Versal, Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze based FPGA designs. Topics include secure and non-secure boot flow including programming the boot device (QSPI, JTAG, SD eMMC, NAND, NOR), bootrom, FSBL, loading of the bitstream, fallback/multi-boot, programming of eFUSEs and BBRAM.
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A board to discuss topics on Artix™-7, Kintex™-7, Spartan™-7, Virtex®-7, Virtex® Family FPGAs and Spartan® Family FPGAs including Zynq-7000 SoCs including device architecture, clocking, SelectIO, signal integrity, packaging, power, and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the Embedded forums.
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Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, SEM IP, Programming cables, Tandem, iMPACT, and Vivado Device Programmer software related topics. Boot for Versal, Zynq Ultrascale+ and Zynq-7000 is not covered here.
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Welcome to the Kria SOM Forum. You can use this forum to discuss any topics surrounding K26 SOM usage, KV260 Vision AI Starter Kit, compatible accessories, carrier card design, SD card images, boot options, Vivado/Vitis design flow, AI models, accelerated applications, and much more. We have a wealth of community and Xilinx knowledge here to help.
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Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs.
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Discuss IP and tools including Chipscope, Integrated Logic Analyzer (ILA), IBERT, VIO, XPE and Power Estimation tools, and others.
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Discuss Topics on all Xilinx IP not included on other boards like BRAM/FIFO, Distributed Logic Generator, ECC, Xilinx Parameterized Macro (XPMs) , CPRI and JESD.
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