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Explorer
Explorer
1,062 Views
Registered: ‎04-19-2018

AXI slave in HLS?

When interfacing an HLS block it's possible to define a port as axi_s, axilite and m_axi. Is it possible to have a slave memory-mapped AXI?

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7 Replies
Voyager
Voyager
1,020 Views
Registered: ‎08-16-2018

Re: AXI slave in HLS?

@satguy

If you look at Fig 1-42, page 90 in UG902 (v2018.2) you will see it's not possible to define an interface as slave AXI....

You can use either ap_memory or bram interface (with an array argument - the index will be the address), implement that memory and access it with dual port or AXI interconnect. This is the way to go if your function needs random access to the array elements (for example FFT or image processing).

If you only need a sequential access to data (use the first value, then the second and so on), It's better to implement the port as ap_fifo

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Scholar u4223374
Scholar
1,014 Views
Registered: ‎04-26-2015

Re: AXI slave in HLS?

s_axilite is a memory-mapped AXI Slave, but only for the AXI Lite protocol. Among other things, this means you can't do burst writes to it.

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Explorer
Explorer
991 Views
Registered: ‎04-19-2018

Re: AXI slave in HLS?

@u4223374

Exactly, for the sake of speed (and the amount to be transferred), I'd like the full AXI.

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Scholar u4223374
Scholar
972 Views
Registered: ‎04-26-2015

Re: AXI slave in HLS?

I don't think it can be done. This is probably because the Zynq 7000 (as far as I know) can't actually generate a burst from its AXI Master ports, so Xilinx never saw the need to implement a full AXI Slave interface.

 

For high performance, I prefer to just leave the data in RAM, put an AXI Master port on the block, and have it pull data from RAM as required. For the AXI Master HLS can easily do burst transfers.

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Explorer
Explorer
952 Views
Registered: ‎04-19-2018

Re: AXI slave in HLS?

@u4223374

Not the zynq, I would never put processors in high speed data flows, but any other AXI stream source

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Scholar u4223374
Scholar
933 Views
Registered: ‎04-26-2015

Re: AXI slave in HLS?

@satguy For a high-performance AXI stream source, it's not a problem - you just use the "axis" interface. The problem is a high-performance memory-mapped AXI source.

 

Realistically, AXI Slave interfaces in HLS are set up as registers or RAM (there's no way to pull the data from the interface as it comes in, without buffering it first). The maximum size of register/RAM is pretty limited simply because the FPGA has a limited amount. This reduces the need for a high-performance AXI slave.

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Contributor
Contributor
918 Views
Registered: ‎03-13-2017

Re: AXI slave in HLS?


@satguy wrote:

When interfacing an HLS block it's possible to define a port as axi_s, axilite and m_axi. Is it possible to have a slave memory-mapped AXI?


What about to use an external module like
    "The AXI Memory Mapped to Stream Mapper IP (axi_mm2s_mapper)" XILINX PG102
Among others, this IP encapsulates AXI4-MM slave interface transactions onto two AXI4-S interfaces.

The IP should expose to the external world an AXI4-MM slave interface and would connect with the HLS IP by means of axi_s only.
The following picture comes from the IP Product Guide.
image.png

The role of the AXI_MM2S (expand) on the right should be played by the HLS IP.

I'm not an expert of AXI4 protocols, I never tried it but let me know what you think about.

 

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