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Contributor
Contributor
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Registered: ‎03-07-2018

Actual latency is more than maximum value of HLS estimation

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Synthesis report gives latency in terms of min and max for my HLS code. When I export this as RTL and implement on FPGA board, actual latency is more than the max value of HLS estimates. My timer starts exactly when HLS IP starts and stops when ap_done of HLS IP goes to '1'. My idea is that actual latency should be some number in between min and max value of HLS estimation. Is this possible that actual latency is even more than max value??

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Scholar u4223374
Scholar
345 Views
Registered: ‎04-26-2015

回复: Actual latency is more than maximum value of HLS estimation

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There are two common causes:

 

(1) Incorrectly specified loop tripcounts. If you specify a loop bound with "#pragma HLS LOOP_TRIPCOUNT min=1 max=10" but the loop actually does 100 iterations, then HLS is going to get the wrong answer. The solution is to give HLS the correct information.

(2) Data access. HLS assumes that AXI transfers happen in one cycle. This may not be the case; an AXI stream can block (either receiving or sending), as can an AXI Master. HLS has no way of knowing how long these might block for, so it ignores that.

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Moderator
Moderator
359 Views
Registered: ‎05-27-2018

回复: Actual latency is more than maximum value of HLS estimation

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Hi @kritika117 ,

    Is there a variable index on your Loop ? Does the value vary a lot?

    There are posibilities that the actual latency is even more than max value. Vivado HLS cannot satisfy the timing requirements for a particular path, it still achieves timing on all other paths. This behavior allows you to evaluate if higher optimization levels or special handling of those failing paths by downstream logic syntheses can pull-in and ultimately satisfy the timing.

Wen

 

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Scholar u4223374
Scholar
346 Views
Registered: ‎04-26-2015

回复: Actual latency is more than maximum value of HLS estimation

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There are two common causes:

 

(1) Incorrectly specified loop tripcounts. If you specify a loop bound with "#pragma HLS LOOP_TRIPCOUNT min=1 max=10" but the loop actually does 100 iterations, then HLS is going to get the wrong answer. The solution is to give HLS the correct information.

(2) Data access. HLS assumes that AXI transfers happen in one cycle. This may not be the case; an AXI stream can block (either receiving or sending), as can an AXI Master. HLS has no way of knowing how long these might block for, so it ignores that.

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Contributor
Contributor
339 Views
Registered: ‎03-07-2018

回复: Actual latency is more than maximum value of HLS estimation

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@wenchen 

Thanks for your quick reply.

Yes, there are 5-6 loops with variable upper bound. This value varies from 0 to 19.

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Contributor
Contributor
337 Views
Registered: ‎03-07-2018

回复: Actual latency is more than maximum value of HLS estimation

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@u4223374 

Thanks for your reply.

Yes, you are correct, these two can be the possible reasons. I am using AXI master interface for receiving/sending the input/output values. 

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