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Contributor
Contributor
7,700 Views
Registered: ‎12-29-2013

Ambiguous Verilog 2001 vs. Verilog 2005 / SystemVerilog $readmemh behavior and Vivado HLS output

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There is a subtle difference in $readmemh behavior between the Verilog 2001 and the newer Verilog 2005 / SystemVerilog standards. Vivado HLS produces code with different meaning in the two versions of Verilog.

 

The syntax for $readmemh is as follows:

 

$readmemh ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;

 

When start_addr and finish_addr are omitted, this is what happens in Verilog 2001 (from sec. 17.2.8 of IEEE Std. 1364-2001):

 

"If no addressing information is specified within the system task, and no address specifications appear within the data file, then the default start address shall be the left-hand address given in the declaration of the memory. [...]"

 

But since Verilog 2005 the behavior is as follows (from sec. 17.2.9 of IEEE Std. 1364-2005, a similar wording is found in IEEE Std. 1800-2012):

 

"If no addressing information is specified within the system task and no address specifications appear within the data file, then the default start address shall be the lowest address in the memory. [...]"

 

So consider code such as the following (actual copy&paste from code generated by Vivado HLS, no address information is included in the data files generated by Vivado HLS):

 

(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];

 

initial begin
    $readmemh("./racalc_mta_racalc_mta_stage1_pdae_data_valid_ram.dat", ram);
end

 

Following Verilog 2001 rules the first word in the data file is loaded into memory location MEM_SIZE-1 (and counting down from there for successive words).

 

But following Verilog 2005 / System Verilog rules the first word in the data file is loaded into memory location 0 (and counting up from there for successive words).

 

I think Vivado HLS should not generate ambiguous code like this. (In generated HLS code it is extremely hard to track down something like that.)

 

Possible solutions to this problem would be: (1) always declare memories from lowest to highest address, i.e. ram[0:MEM_SIZE-1] instead of ram[MEM_SIZE-1:0] and/or (2) always call $readmemh with explicit values for start_addr and finish_addr.

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Xilinx Employee
Xilinx Employee
13,450 Views
Registered: ‎10-24-2013

Re: Ambiguous Verilog 2001 vs. Verilog 2005 / SystemVerilog $readmemh behavior and Vivado HLS output

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Hi @cliffordwolf

 

Filed CR#948580 for the factory to work on this issue.

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
13,451 Views
Registered: ‎10-24-2013

Re: Ambiguous Verilog 2001 vs. Verilog 2005 / SystemVerilog $readmemh behavior and Vivado HLS output

Jump to solution

Hi @cliffordwolf

 

Filed CR#948580 for the factory to work on this issue.

Thanks,Vijay
--------------------------------------------------------------------------------------------
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