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Observer
Observer
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Registered: ‎07-01-2020

Array operations

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Hi,

How could be  possible to implement the design shown in attached video?

in the video the arrays are 600 samples each, but i would go for bigger arrays as possible

i'm planning to use a zybo z7 board

The visual side is only in purpose of showing the design, i just need the calculus on arrays, without visualization

 

Kind regards

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Advisor
Advisor
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Registered: ‎04-26-2015

Yes, you can absolutely do them in DDR. Or you can skip RAM and just calculate them on-the-fly. A CORDIC sine calculation can be done in a small number of clock cycles, and mixing that with a square wave should not be difficult.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014

Hi @ViennaAudio 

 

Can you please elaborate on the specifications that you want to implement here. What is the significance of cross input and arrays in the design?

 

-Shreyas

 

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Observer
Observer
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Registered: ‎07-01-2020

Hi,

 

the resultant array from crossing inputs is going to be the wavetable for a wavetable audio oscillator, achieved with a simple lookup table tecnique.

arrays should have 24bits value and 16384 values if possible.

the operation control i activate in video using the mouse should translate into an external input from adc

 

the less latency for operations the better

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Advisor
Advisor
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Registered: ‎04-26-2015

Yes, that should be easy. The Zynq 7010 (as used on the Zybo) has 60 36Kb block RAMs. You would most likely use them in 16384x2-bit mode, which means that your 24-bit data will occupy twelve of them - 20% of what is available on the chip.

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Observer
Observer
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Registered: ‎07-01-2020

Thanks a lot,

but said that in my design there are many similar operations, could be the ddr be used instead of block ram for such task?

 

otherwise using only block ram  i should reduce the array values number to 4096 i guess

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Advisor
Advisor
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Registered: ‎04-26-2015

Yes, you can absolutely do them in DDR. Or you can skip RAM and just calculate them on-the-fly. A CORDIC sine calculation can be done in a small number of clock cycles, and mixing that with a square wave should not be difficult.

View solution in original post

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Observer
Observer
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Registered: ‎07-01-2020

Thx a lot,

the morphing between sine and square in the video is just an example.

for many reasons, i cannot go for different design as the one you mention, i must work with arrays.

 

I would use block memory for 6 rom arrays and then the ddr for all the rest.

could you help me to implement the ddr memory arrays? is there any IP that could be ok for that design?

Could i instance copies of that block and run it in parallel?

Thx a lot again

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Observer
Observer
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Registered: ‎07-01-2020

accepted solution

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Advisor
Advisor
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Registered: ‎04-26-2015

You don't really need an IP core for this. The process is:

 

(1) Create a HLS block with either a bunch of arrays as inputs/outputs on the top-level module, or a single large array that you split up internally.

(2) Specify the m_axi interface for the array/arrays.

(3) When you're doing the Vivado block diagram, plug the HLS AXI Master port into any of the four Zynq PS HP AXI Slave ports.

(4) Make sure that the processor doesn't mess with whatever memory addresses you've chosen to use for the arrays (easy if it's bare-metal, not much harder if it's running Petalinux).

 

Reads/writes from/to those arrays will automatically go to DDR RAM via the CPU's RAM controller. Random reads/writes will be slow, but for audio I doubt it'll be an issue.

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