Axi master memcpy reading does not work on Cosimulation (Vitis HLS 2020.1)

[namabo]

Hi everybody,

I running the cosimulation for the example design of Xilinx repo:

https://github.com/Xilinx/HLS-Tiny-Tutorials

The example is:  interface_axi_master

I made a small modification to that example following the code:

void example(volatile int *a){
  
#pragma HLS INTERFACE m_axi port=a depth=50
  
  int i;
  int buff[50];
  
  //memcpy creates a burst access to memory
  //multiple calls of memcpy cannot be pipelined and will be scheduled sequentially
  //memcpy requires a local buffer to store the results of the memory transaction

  
  for(i=0; i < 50; i++){
    buff[i] = buff[i] + 100;
  }
  
  memcpy((int *)a,buff,50*sizeof(int));
  memcpy(buff,(const int*)a,50*sizeof(int));
}

 I the original example the instructions flow is a:

READ (memcpy)

MODIFICATION (for cycle)

WRITE(memcpy)

My modification,as listed in the code posted above, consists on:

MODIFICATION (for cycle)

WRITE(memcpy)

READ (memcpy)

Basically I write on the AXI master interface and then read back the data.

If I make a Cosimulation in Vitis HLS I don't get the reading operation, and the writing one is with WDATA = 'X' as show in the picture:

I think this is a really simple example writing and then reading, what's wrong?

Thank you for your help

[dsakjl · Accepted solution]

Hi @namabo ,

you are working with the buff variable not initialized. Setting buff as static solve the problem.

Cheers.

[namabo]

Thank you @dsakjl ,

this solve the proble!