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Visitor
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Registered: ‎12-02-2014

Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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Thanks for your help.I have a problem with Vivado HLS. I implemented a design using C language with Vivado HLS. And the co-sim also passed. But when I used this ip in Vivado, I got wrong outputs. Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-22-2011

Re: Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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When you use the export RTL feature to export the IP package, Vivado HLS automatically creates a Vivado project.

- This Vivado project is provided in the impl/verilog and impl/vhdl sub-directories.

- This Vivado project is provided to give designers more familiar with an RTL evironment an easy way to analyze their design

- This Vivado project is not meant as a means of (or path for) exporting your RTL. In this project, the VIvado HLS design is the top-level and has no IO buffers and so it cannot fully routed: it's provided only for analysis. To use the HLS ouptut in a larger design you should still use the IP package or design checkpoint.

 

If you have first simulated your desing using RTL co-sim, this Vivado project will also contain an RTL testbench. It's not a re-write of the C testbench, but rather just a collection of the input (and expected output) vectors provided in Verilog and/or VHDL. Note, if you have not run RTL co-sim prior to Export RTL this project will only contain the RTL design files.

 

If it's just for analysis, you may be able to open this project and edit the Verilog or VHDL test bench to suit you needs.Or simply just run the pure RTL sim from within Vivado and peform your analysis. 

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Contributor
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Registered: ‎10-06-2013

Re: Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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As your C/RTL Co-simulation works fine that means generated RTL is functionally okay. So if you try to check using the instrumented testbench from C testbench, you will get same result. But when you are trying to use this IP furher, just check whether you have done proper interface synthesis to use the IP or say you must have proper communication. Like in some FPGA SoC architecture, there are processor-system (PS) as well as programmable logic(PL). So to use IP, implemented on PL from the PS, you must have interfaces. Vivado HLS is pretty good in handling interface synthesis using fifo, memory etc.

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Moderator
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Registered: ‎04-17-2011

Re: Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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You can write a top level testbench in Vivado and perform a Post-Synthesis simulation which would include the IP and any other glue logic you have.
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-22-2011

Re: Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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When you use the export RTL feature to export the IP package, Vivado HLS automatically creates a Vivado project.

- This Vivado project is provided in the impl/verilog and impl/vhdl sub-directories.

- This Vivado project is provided to give designers more familiar with an RTL evironment an easy way to analyze their design

- This Vivado project is not meant as a means of (or path for) exporting your RTL. In this project, the VIvado HLS design is the top-level and has no IO buffers and so it cannot fully routed: it's provided only for analysis. To use the HLS ouptut in a larger design you should still use the IP package or design checkpoint.

 

If you have first simulated your desing using RTL co-sim, this Vivado project will also contain an RTL testbench. It's not a re-write of the C testbench, but rather just a collection of the input (and expected output) vectors provided in Verilog and/or VHDL. Note, if you have not run RTL co-sim prior to Export RTL this project will only contain the RTL design files.

 

If it's just for analysis, you may be able to open this project and edit the Verilog or VHDL test bench to suit you needs.Or simply just run the pure RTL sim from within Vivado and peform your analysis. 

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Moderator
Moderator
10,195 Views
Registered: ‎04-17-2011

Re: Can I use the testbench generated by Vivado HLS Co-sim to test the project after systhesis in Vivado?

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@exirrl Please feel free to close this topic by marking the answer which helped you as an Accepted Solution. It is helpful for other community members.
Regards,
Debraj
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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