UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant futuristic
Participant
711 Views
Registered: ‎11-02-2017

Co-Simulation Fail

Folks, 

I am getting a Co-Simulation fail for my design. 

It is not straight forward to trace the error as different Vivado HLx version return different error messages. 

Vivado 2017.2:  Simulation passes. 

CoSimulation failes with the follwoing error: 

[SIM-360] Aborting co-simulation: C TB simulation failed.
[SIM-320] C TB testing failed, stop generating test vectors. Please check C TB or re-run cosim.
[SIM-4] *** C/RTL co-simulation finished: FAIL ***

Vivado 2018.2 and 2018.3: simulation passes. 

CoSimulation failes with the following error: (Even example designs fail for CoSimulation :( )

 

WARNING: [COSIM 212-369] AXI_master port 'a' has a depth of '123456'. Insufficient depth may result in simulation mismatch or freeze.

ERROR: [COSIM 212-317] C++ compile error. ERROR: [COSIM 212-321] EXE file generate failed. ERROR: [COSIM 212-321] EXE file generate failed. ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors

So, anyone had the same problem and how to solve it? 

Cheers,

 

0 Kudos
2 Replies
Moderator
Moderator
672 Views
Registered: ‎05-31-2017

Re: Co-Simulation Fail

Hi @futuristic,

can you please check and confirm if the testbench array size and design array size is the same, this might be the case for the co-simulation failure. 

0 Kudos
Participant futuristic
Participant
662 Views
Registered: ‎11-02-2017

Re: Co-Simulation Fail

@shameeraYes, they are the same.  My code follows similar format as below.

Testbench:  

a = (int*)malloc(123456);

Design Interface:

#pragma HLS INTERFACE m_axi port = a depth=123456 offset = slave bundle = xx register

 

0 Kudos