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Observer noahhuetter
Observer
2,536 Views
Registered: ‎06-27-2017

Concurrent AXI read and write

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Hi all

 

This is my scenario: An IP block gets data from memory via m_axi (not burst because of non linear addressing) and streams it out via axi stream. Simultaneously it should read data from another stream and store it in memory using the same m_axi port.

 

Simplified code:

 

void controller_top(volatile uint8_t *memp, AXI_STREAM &outData, AXI_STREAM &inData)
{
//#pragma HLS DATAFLOW
#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE axis register reverse port=inData
#pragma HLS INTERFACE axis register forward port=outData
#pragma HLS INTERFACE m_axi depth=1168 port=memp offset=off

	mem_to_stream(memp, outData);
	stream_to_mem(memp, inData);
}

Problem: The dataflow checking fails with Cannot communicate over function parameter. In my case I don't need to communicate over the functions. One writes to memp the other reads from memp.

 

Question: Does this use-case require two m_axi ports (one for write, one for read) albeit m_axi is capable of concurrent read and write transactions?

 

Thanks in advance!

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Scholar u4223374
Scholar
2,931 Views
Registered: ‎04-26-2015

Re: Concurrent AXI read and write

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I'm 99% sure that you do need two AXI Masters. HLS only connects an interface to one block at a time. Either your AXI Master is connected to mem_to_stream, or it's connected to stream_to_mem. As such, they can't run in parallel unless you have a second AXI Master handy.

 

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7 Replies
Scholar u4223374
Scholar
2,932 Views
Registered: ‎04-26-2015

Re: Concurrent AXI read and write

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I'm 99% sure that you do need two AXI Masters. HLS only connects an interface to one block at a time. Either your AXI Master is connected to mem_to_stream, or it's connected to stream_to_mem. As such, they can't run in parallel unless you have a second AXI Master handy.

 

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Xilinx Employee
Xilinx Employee
2,499 Views
Registered: ‎07-18-2014

Re: Concurrent AXI read and write

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Hi @noahhuetter

can you give a try to following code change to use same m_axi interface?

 

void controller_top(volatile uint8_t *memin, volatiel uint8_t *memout, AXI_STREAM &outData, AXI_STREAM &inData)
{
//#pragma HLS DATAFLOW
#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE axis register reverse port=inData
#pragma HLS INTERFACE axis register forward port=outData
#pragma HLS INTERFACE m_axi depth=1168 port=memin offset=off
#pragma HLS INTERFACE m_axi_depth=1168 port=memout offset=off mem_to_stream(memin, outData); stream_to_mem(memout, inData); }
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Observer noahhuetter
Observer
2,487 Views
Registered: ‎06-27-2017

Re: Concurrent AXI read and write

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Thank you guys! Mi intention here is to only use one m_axi interface. I am using a workaround now that reads the required data into a memory first, then executes the transaction via stream and then stores it back via m_axi.

 

void controller_top(volatile uint8_t *memp, AXI_STREAM &outData, AXI_STREAM &inData)
{
#pragma HLS DATAFLOW
#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE axis register reverse port=inData
#pragma HLS INTERFACE axis register forward port=outData
#pragma HLS INTERFACE m_axi depth=1168 port=memp offset=off

	static uint8_t in_mem[IN_LINE_SIZE];
	static uint8_t out_mem[OUT_SIZE];

	// copy input data
	memcpy((void*)in_mem,(const void*)(&memp[IN_MEMORY_BASE]),IN_LINE_SIZE*sizeof(uint8_t));

	mem_to_stream(in_mem, outData);
	stream_to_mem(out_mem, inData);

	// copy output data
	memcpy((void*)(&memp[OUT_MEMORY_BASE]),(const void*)out_mem,OUT_LINE_SIZE*sizeof(uint8_t));
}

I is also faster than my initial approach because of the burst reads. Thanks anyways!

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Scholar u4223374
Scholar
2,478 Views
Registered: ‎04-26-2015

Re: Concurrent AXI read and write

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@heeran Can you please explain how that code would create a single AXI Master? I thought the only way to merge AXI Masters was to use the "bundle" option in the pragma. If there's another way to do it - and especially if the other approach allows for concurrent access - then I'd definitely like to know about it!

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Xilinx Employee
Xilinx Employee
2,432 Views
Registered: ‎07-18-2014

Re: Concurrent AXI read and write

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Hi @u4223374,

 

yes, you are correct. Using same bundle name, two separate ports(function arguments) can be associated to single master interface as below:

 

void controller_top(volatile uint8_t *memin, volatiel uint8_t *memout, AXI_STREAM &outData, AXI_STREAM &inData)
{
//#pragma HLS DATAFLOW
#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE axis register reverse port=inData
#pragma HLS INTERFACE axis register forward port=outData
#pragma HLS INTERFACE m_axi depth=1168 port=memin offset=off bundle=gmem0
#pragma HLS INTERFACE m_axi_depth=1168 port=memout offset=off bundle=gmem0
mem_to_stream(memin, outData); stream_to_mem(memout, inData); }


 

We have similar type of design and got parallel read and write. 

 

-Heera

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Participant twoism_
Participant
1,531 Views
Registered: ‎12-30-2015

Re: Concurrent AXI read and write

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Hi @heeran,

I've tried to follow the approach you suggested to bundle two AXI master ports, but the design still results in two separate AXI master interfaces with the follwing warnings:

WARNING: [XFORM 203-803] Cannot bundle argument 'mem_in' (test_master_64/src/master64.cpp:62:1) to m_axi port 'mem_bus' since its offset mode is off.
WARNING: [XFORM 203-803] Cannot bundle argument 'mem_out' (test_master_64/src/master64.cpp:64:1) to m_axi port 'mem_bus' since its offset mode is off.

To my best knowledge, the only way to bundle two (or more) AXI master ports into a single AXI master interface is by using the "offset=slave" directive:

#pragma HLS INTERFACE m_axi offset=slave port=mem_in bundle=hostmem
#pragma HLS INTERFACE s_axilite port=mem_in bundle=control
#pragma HLS INTERFACE m_axi offset=slave port=mem_out bundle=hostmem
#pragma HLS INTERFACE s_axilite port=mem_out bundle=control

Do you know if it's possible to bundle two (or more) master ports into a single master interface without using the "offset=slave" directive? It would be beneficial for my PR design since I need multiple modules with the same "standard" interface.

Thanks in advance.


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Xilinx Employee
Xilinx Employee
1,372 Views
Registered: ‎07-18-2014

Re: Concurrent AXI read and write

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Hi @twoism_,

I am not sure if we can bundle two master ports to single master interface without offset=slave. 

I will let others to comment on this. 

-Heera

 

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