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Explorer
Explorer
1,845 Views
Registered: ‎05-21-2017

Confusion regarding the axis interface

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Hello,

 

my design uses an input stream to bring the data in fast using the AXI Stream interface, stores some of the input data into BRAMs to process it in a random way, writes the results to BRAMs, and finally uses an output stream to send the data out.

 

My streams are defined in the following way:

 

#include <hls_stream.h>
#include <ap_axi_sdata.h>

typedef ap_axiu<16,1,1,1> data_axis_t;

void hw_foo( hls::stream<data_axis_t> &inputs_strm, hls::stream<data_axis_t> &output_strm)

 

And I use the following directives:

 

set_directive_interface -mode axis -register_mode off "hw_conv" inputs_strm
set_directive_interface -mode axis -register_mode off "hw_conv" output_strm

 

when the axis interface "register_mode" is set to "both" C/RTL Cosimulation fails

with output reporting that the first element that I received from my output stream is wrong when it is compared to the expected value

 

BUT

 

when the axis interface "register_mode" is set to "off" C/RTL Cosimulation passes!

 

I don't understand this behavior and I'm also worried because I don't define in any way the depth of the axis fifos.

 

Finally when I push data into my streams I do it in the following way:

 

data_axis_t tmp;

for ( lindex_t n = 0; n < N; n++ )
{

	tmp.data = data_in[n].V;
	inputs_strm << tmp;

}

So, what is the proper way to define and use the axis interface?

 

 

 

Cheers,

Panos

 

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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Scholar u4223374
Scholar
2,631 Views
Registered: ‎04-26-2015

Re: Confusion regarding the axis interface

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I had a problem very similar to this (enabling AXIS registers breaks the block) way back in (if I recall correctly) HLS 2016.1. Solution was to disable registers, and I've done that in every block since - with no problems.

 

I would advise simply leaving off the registers. If you're really struggling to meet timing then you can always add an external AXIS register slice.

4 Replies
Scholar u4223374
Scholar
2,632 Views
Registered: ‎04-26-2015

Re: Confusion regarding the axis interface

Jump to solution

I had a problem very similar to this (enabling AXIS registers breaks the block) way back in (if I recall correctly) HLS 2016.1. Solution was to disable registers, and I've done that in every block since - with no problems.

 

I would advise simply leaving off the registers. If you're really struggling to meet timing then you can always add an external AXIS register slice.

Explorer
Explorer
1,825 Views
Registered: ‎05-21-2017

Re: Confusion regarding the axis interface

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Thank you @u4223374 for the quick reply!

 

I use Vivado HLS 2017.2.

 

What about the axis INTERFACE "depth" option - will my block have any problems when I'll attach it to my application?

 

I just use the axis interface to bring in the data fast and write them to BRAMs. In the case I had to use a data stream internally, should I consider to set the fifo depth of that internal stream?

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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Scholar u4223374
Scholar
1,820 Views
Registered: ‎04-26-2015

Re: Confusion regarding the axis interface

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@pmousoul I honestly don't know what the "depth" option does on an AXIS interface; I've never used it. UG902 does not seem to say anything about it. My guess is that it just gets ignored.

 

You shouldn't need to set the FIFO depth of an internal stream unless you're using dataflow - and even then the application you've got doesn't sound like it'll really benefit from a FIFO. The main purpose of the FIFO is to handle situations where the transmitting block is ready to write while the receiving block isn't ready to read. In this case the receiving block is just block RAM, and block RAM will always be ready.

Explorer
Explorer
1,801 Views
Registered: ‎05-21-2017

Re: Confusion regarding the axis interface

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@u4223374

 

One last question.

 

Is it possible to use an input stream and write the incoming data to BRAM two elements in each cycle?

Or any other way that can be used to transfer data as fast as possible, e.g. taking advantage of the fact that my data elements are 16-bit wide and that AXI Stream can move lets say 64/128 at one cycle?

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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