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Observer
Observer
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Registered: ‎09-16-2020

Connecting custom IP to Zynq ultrascale PS

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Hi everyone, I'm a newbie in Vivado development. 

I'm doing my first experiments with tutorials and online material and I needed some help with my small "project", in particular, how to connect my custom IP (created with Vivado HLS) to my Ultrascale board PS (part code: xczu3eg-sbva484-1-e).

My final goal is to import everything inside PYNQ and execute my simple code from there.

My custom IP part has the following C code in HLS:

 

// NO SYSTEM CALLS! NO STRING, NO STDIO ECC...!

typedef struct data{   // Declare PERSON struct type
    int age;
    int sex;// 1 male- 0 female
    //float weight;
}input_data;

// Classes: young_male, old_male, young_female, old_female
// If i pass only the pointer, the code doesn't actually know the real size of the array.
// In standard programming, it's no problem, since as soon as I manage it properly, I dont have any segfault
// In Vivado, since i need to build real "circuits" and connection, it needs to know the size of the incoming array
// So i have to pass my array specifying also the size

void simple_tree(input_data *input, int result[4]){ //input is a pointer to a data struct

	if(input->age > 50)
	{
		if(input->sex==1)
		{
			result[0]=1; //old male;
		}
		else{
			result[1]=1; //old_female;
		}
	}
	else{
		if(input->sex==1){
			result[2]=1; //young_male;
		}
		else{
			result[3]=1; //young_female;
		}
	}

}

 

Which is a simple function that receives a struct and classifies the user in a decision tree approach.

This is my test bench C function: 

#include <stdio.h>



typedef struct data{   // Declare PERSON struct type
    int age;
    int sex;// 1 male- 0 female
    //float weight;
}input_data;

void simple_tree(input_data *input, int result[4]);

int main()
{
	int result[4];
	for(int i=0; i<4;i++){
		result[i]=0;
	}
	input_data data;
	data.age=20;
	data.sex=1;
	simple_tree(&data, result);

	for(int i=0; i<4;i++){
			printf("%d",result[i]);
		}
	printf("\nfinished main");
	printf("\ntest changes \n");


	return 0;




}

 I'm able to simulate, synthesize, export and co-simulate my code and works fine.

Now, once I'm done with HLS, I moved to Vivado and i started to implement my hardware design using the block design. I successfully imported both my board and my custom IP and this is what i get in the end: 

Vivado designVivado design

Unfortunately now I'm quite lost. How should I connect my 2 elements? I followed many tutorials online but I can't figure out what I need.

My final goal is to connect the 2 parts (Zynq ultrascale+ and my IP), esport my design, import it into PYNQ and then simply perform the same function of my testbench but using python on my Zynq board.

So, basically, i'll import my overlay in PYNQ, instantiate my data and call the function "simple_tree" which will "classify" my user. 

Sorry for the basic questions, but I'm starting now exploring this amazing world  

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Scholar
Scholar
191 Views
Registered: ‎03-28-2016

@mattiasu96 

You need add directives to your HLS project to tell HLS that you want the top-level ports to be part of an AXI4-Lite interface.  Once exported, the IP can be connected to the PS via the AXI4_Lite interface.

Take a look at UG902 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug902-vivado-high-level-synthesis.pdf) and search for "AXI4-Lite".

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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2 Replies
Highlighted
Scholar
Scholar
192 Views
Registered: ‎03-28-2016

@mattiasu96 

You need add directives to your HLS project to tell HLS that you want the top-level ports to be part of an AXI4-Lite interface.  Once exported, the IP can be connected to the PS via the AXI4_Lite interface.

Take a look at UG902 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug902-vivado-high-level-synthesis.pdf) and search for "AXI4-Lite".

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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Highlighted
Observer
Observer
178 Views
Registered: ‎09-16-2020

So I should add something like:

 

#pragma HLS INTERFACE s_axilite port=input bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=result bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS

 

to my top level function (which is simple_tree) declaration in HLS? 

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