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Observer andrewsi
Observer
892 Views
Registered: ‎09-09-2017

Cosim fails but no error message tells what's wrong...

I'm using 2018.3.  My normal C testbench runs to completion with no errors and the synthesis seems to be fine.  However, when I run the cosimulation, after it completes running the ordinary C simulation, I get the following.  I am at a loss to determine what the problem is.  The design has what I believe should be a sufficient DEPTH parameter for the AXI interface, and I have in fact raised it previously to the point where a SIGSEGV was generated, and then reduced it again.

Where would one begin troubleshooting this problem?

INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
11
    while executing
"source C:/Users/andrewsi/OneDrive/fpgaproducts/Vivado/mandelbrot/AXI/cosim.tcl"
    invoked from within
"hls::main C:/Users/andrewsi/OneDrive/fpgaproducts/Vivado/mandelbrot/AXI/cosim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

 

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9 Replies
Teacher xilinxacct
Teacher
880 Views
Registered: ‎10-23-2018

Re: Cosim fails but no error message tells what's wrong...

@andrewsi

The '[COSIM 212-211]' message indicates the testbench only had one call to it.. is that correct?

If there is a second call, it would seem to be there.

Also, Does the testbench return a 0? If not, that would raise a false failure.

Hope that helps

If so, marks as solution accepted. Kudos also welcomed. :-)

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Observer andrewsi
Observer
876 Views
Registered: ‎09-09-2017

Re: Cosim fails but no error message tells what's wrong...

Correct. There is no second call to the TestBench. I am still confused about where the problem is.

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Observer andrewsi
Observer
875 Views
Registered: ‎09-09-2017

Re: Cosim fails but no error message tells what's wrong...

 Oh yes, and the TestBench does return zero when it’s completed. 

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Teacher xilinxacct
Teacher
848 Views
Registered: ‎10-23-2018

Re: Cosim fails but no error message tells what's wrong...

@andrewsi

Is there any code between the call and the end of the testbench? Or any code that is executed at program exit (e.g. destructors, etc).. If so, I would focus there, as I 'think' that since you see the the last WARNING, seem to indicate it made it passed that point.

Hope that helps

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Observer andrewsi
Observer
838 Views
Registered: ‎09-09-2017

Re: Cosim fails but no error message tells what's wrong...

There is some that prints outputs after the call has completed.  However, the sim did not run nearly long enough to have reached that point, the actual simulation of the IP never seems to have occurred before it fails out.

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Observer andrewsi
Observer
801 Views
Registered: ‎09-09-2017

Re: Cosim fails but no error message tells what's wrong...

I think I have finally found a solution. Within the IP itself, there is both an AXI Slave interface for input registers and an AXI Master interface that is used to access an array for the IP's output data. When failing, there was a directive to to expose an offset parameter on the slave for use in writing to the output array, and to bundle that parameter in with the existing AXI slave interface.

As soon as I remove those options from the AXI Master directive, the cosimulation runs without the immediate failure that I described above.

Personally, I think this should be filed as a bug to the engineering team.

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Observer adefan
Observer
484 Views
Registered: ‎04-13-2016

Re: Cosim fails but no error message tells what's wrong...

You are right. I am working on a test project. the original IO directive is

#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
#pragma HLS INTERFACE m_axi depth=2073600 port=image_out offset=slave bundle=CTRL_BUS
#pragma HLS INTERFACE m_axi depth=2073600 port=image_in offset=slave bundle=CTRL_BUS

#pragma HLS DATAFLOW

It generates the same COSIM error.

after the directive change to

#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
#pragma HLS INTERFACE m_axi depth=2073600 port=image_out offset=slave bundle=DATA_BUS
#pragma HLS INTERFACE m_axi depth=2073600 port=image_in offset=slave bundle=DATA_BUS
#pragma HLS DATAFLOW

THe COSIM passed.

set offset = off or direct also avoid COSIM fail.

But Don't know the consequnce of these directive changes on the Synthesis.

 

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Observer andrewsi
Observer
468 Views
Registered: ‎09-09-2017

Re: Cosim fails but no error message tells what's wrong...

It shouldn’t have much effect on synthesis other than the starting address that the master interface accessed within the mapped memory region.

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Observer adefan
Observer
445 Views
Registered: ‎04-13-2016

Re: Cosim fails but no error message tells what's wrong...

YES. Got the expected function. use the diffrent bundle name is the right solution.

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