05-14-2018 08:40 AM
I have a custom IP which generates 32 bit data continuously and stores it in slv_reg0 (base address 0x43c00000) register created by the IP. I now want to transfer these data to the PC via ethernet.I have a python program running in the pc which captures these data and stores it in file. Any suggestion on how to proceed?
I am newbie and have no idea idea how to proceed. Please help..
Thanks in advance
05-14-2018 10:51 AM
I think the easiest way to transfer data from PL to a PC is to use one of the Ethernet cores from FPGA-Cores.com.
It has a simple AXI4 Stream interface to TCP. In the PC you simply opens a TCP socket and reads the stream.
It is very simple to use and no cost :-)
Xilinx has AXI4 Stream width converters so you can convert the stream from 32 to 8 bits width or you do a simple process writing bytes from the 32 bits.
05-15-2018 02:54 AM
Thanks for your reply. Can you tell me on how to use this fpga core in my project. I downloaded the .vhd file from the website and added as a source to the project. Can you please tell what to do next?
05-15-2018 03:12 AM
Will it be easier if I read the register (slv_reg0, 0x43c00000) from PS and then transfer it to pc? Any suggestion how to carry out this?
05-15-2018 03:54 AM
You need to download the netlist also. The VHDL is only component declaration.
There is a tutorial that you can look at.
Look at this tutorial: