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Anonymous
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Detailed timing information of how much latency each sub-component takes (SDAccel & Vivado HLS)

Hi Everyone,

 

I'm currently working on an FPGA design using SDaccel (and Vivado HLS). My design have several sub-components, and the latency (clock cycles) of each sub-component would depend on the input data at runtime (Therefore Vivado HLS analysis window would not be able to give me exact latency values). How do i measure the timing of each component in my design, so i can figure out where my bottlenecks are?

 

I found a pragma directive (pragma SDS trace), but i'm not sure how to use it to give me a detailed view of what is happening in the system during execution of different inputs.

 

Are there pragmas in Vivado_HLS that allow this? If so, How do i use them?

 

Thanks

W

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jprice
Scholar
Scholar
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Registered: ‎01-28-2014

There may be a more official way, but I'm not aware of it if so. I just create my own RTL testbench around the HLS code. Typically your top level names are preserved in the hierarchy and each function usually has a ap_ctrl interface so you can observe starts, dones, inputs and outputs. This can be a bit annoying with machine generated code but it's not been to bad. 

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Anonymous
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Thanks jprice
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