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Observer tobinhall
Observer
1,535 Views
Registered: ‎09-08-2017

Detecting axi writes with AP_none

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I have 2 scenario that seem to have the same root issue/requirement.  Because I am building an engine and not a algorithm accelerator, I am using AP_none.

 

1. Autoresetting bit using an Axi slave port.  APU sets a bit and HLS clears it.

 

2. Wait for input HLS comes to a point where Data is required from the APU before proceeding and I don't want stale data. (this is sort of a Variant of #1 as I could Write some uninitialized value and wait for it to change.)

 

I have seen some solutions for older versions of HLS that appear to implement memory, but I'm not sure that they are done the same way on 2017.1.

 

Thanks,

 

Tobin. 

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Voyager
Voyager
2,085 Views
Registered: ‎06-24-2013

Re: Detecting axi writes with AP_none

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Hey Tobin,

 

2 single writes are NOT preferred in attempting to signal HLS.

I don't think HLS provides other AXI Lite interfaces or handshakes ...

 

Probably the easiest way is to create a simple AXI Lite slave which maps each write/read transaction to the typical HLS bus interface with handshake. This way you can still connect everything in block design and a single write/read will trigger the HLS generated IP.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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6 Replies
Observer tobinhall
Observer
1,529 Views
Registered: ‎09-08-2017

Re: Detecting axi writes with AP_none

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Just to clarify I am using AP_ctrl_none and need an axi slave port/address to perform the function.
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Voyager
Voyager
1,494 Views
Registered: ‎06-24-2013

Re: Detecting axi writes with AP_none

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Hey Tobin,

 

I'm not sure I understand what you want to do. Maybe you can give an example?

 

Anyway, the following HLS code creates AXI Lite in/out ports with handshake ...

#include <ap_int.h>

typedef ap_uint<32> reg_t;

void slave(reg_t *I, reg_t *Q) {
    #pragma HLS INTERFACE s_axilite port=I,Q
    #pragma HLS INTERFACE ap_hs port=I
    #pragma HLS INTERFACE ap_vld port=Q
    #pragma HLS INTERFACE ap_ctrl_none port=return

    *Q = *I;
}

... note that this will result in the following registers ...

-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of I_V
--        bit 31~0 - I_V[31:0] (Read/Write)
-- 0x14 : Control signal of I_V
--        bit 0  - I_V_ap_vld (Read/Write/COH)
--        bit 1  - I_V_ap_ack (Read)
--        others - reserved
-- 0x18 : Data signal of Q_V
--        bit 31~0 - Q_V[31:0] (Read)
-- 0x1c : Control signal of Q_V
--        bit 0  - Q_V_ap_vld (Read/COR)
--        others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Observer tobinhall
Observer
1,488 Views
Registered: ‎09-08-2017

Re: Detecting axi writes with AP_none

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The control signals here are of the APU, not for HLS.

Here I(0x10) and Q(0x18) are different Axi Addresses. I need them to control the same address, like memory. In other words Can HLS write I? (APU Sets I HLS clears I).

To put it another way, can HLS detect a write of the same value to the same address from the APU's perspective? (think of a self resetting register that changes on read or write such as many interrupt flag implementations)
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Observer tobinhall
Observer
1,483 Views
Registered: ‎09-08-2017

Re: Detecting axi writes with AP_none

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In my particular application I am trying to have the APU repeatedly atomically signal HLS. 2 single writes is are preferred for performance reasons.
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Observer tobinhall
Observer
1,481 Views
Registered: ‎09-08-2017

Re: Detecting axi writes with AP_none

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eye!!! my typing is getting in the way... 2 single writes are NOT preferred in attempting to signal HLS
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Voyager
Voyager
2,086 Views
Registered: ‎06-24-2013

Re: Detecting axi writes with AP_none

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Hey Tobin,

 

2 single writes are NOT preferred in attempting to signal HLS.

I don't think HLS provides other AXI Lite interfaces or handshakes ...

 

Probably the easiest way is to create a simple AXI Lite slave which maps each write/read transaction to the typical HLS bus interface with handshake. This way you can still connect everything in block design and a single write/read will trigger the HLS generated IP.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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