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jasonjohnson196
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Registered: ‎04-17-2013

Does Vivado HLS support software/hardware co-simulation?

We know that Vivado HLS can be used for verification of the generated HDL via simulation (that is executed entirely on the PC- presumably by invoking ModelSim or ISE simulator). But does Vivado support mixed software/hardware co-simulation? In other words can you run a co-simulation with some tasks running on the actual FPGA and some on the host PC (much like CUDA C with NVidia GPUs). We are quite confident that we can convert existing C or Matlab algorithms into HDL (VHDL or Verilog) either via HLS tools (like Vivado) or manually. But we are not confident that we can manually set up a software/hardware interface that can enable the interaction of a host PC with the FPGA(s) on a development board for co-simulation purposes.

 

We know that Xilinx System Generator (XSG) can achieve this sort of “FPGA in the loop” co-simulation (inside Simulink of course) and that this can accelerate to some degree the speed of execution. I guess that importing Vivado-generated HDL modules into Xilinx System Generator “black boxes” is possible. But, as we all know, the bandwidth of the communication link is usually the bottleneck; and unfortunately XSG cannot support PCI-Express connectivity (which could minimise the problem) and -as Xilinx has admitted- nor will do in the future. Also XSG cannot support co-simulation with complex multi-FPGA boards.

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debrajr
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Registered: ‎04-17-2011

Refer: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug897-vivado-sysgen-user.pdf if it helps. Vivado HLS doesnt support Hardware Co-Simulation.

Regards,
Debraj
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jasonjohnson196
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Hi Debraj,

 

Thanks for your response. In the market of HLS tools there are some that can support mixed software/hardware co-simulation. These, however, are not as good or efficient as Vivado in translating C code to HDL. But since it is possible to import your own HDL functions into these tools I am wondering whether Vivado-generated HDL can be imported to them. Or is Vivado-generated code completely proprietary? It should be noted that these tools can be configured to use Xilinx ISE for synthesis and that the target FPGA chips will be Xilinx ones. Sorry for making reference to rival products in your forum but if Vivado cannot offer entirely what we want we need to think about combining it with other tools.

 

Thanks in advance,

Jason

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debrajr
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Registered: ‎04-17-2011

Hi Jason,

If you prefer to use Vivado, you have an option to Export RTL in Vivado HLS. This would create a zip file which packages your generated HDL from C as an IP. Next, you can add this IP to Vivado and it would be listed in the IP Catalog. Further, you can add it as a block in your design and then perform co-simulation. This is the recommended flow for RTL/EDK & Sysgen designs in HLS.

Regards,
Debraj
Regards,
Debraj
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ywu
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Registered: ‎11-28-2007

I suggest you take a look at the two doucments below on how to use HLS to build HW accelators and use them with SW. Please let us know if it works for you.

 

XAAP1167: Accelerating OpenCV Applications with Zynq using Vivado HLS Video Libraries

 

UG871: Vivado Design Suite Tutorial: High-Level Synthesis : Using HLS IP in a Zynq Processor Design

 


@jasonjohnson196 wrote:

Hi Debraj,

 

Thanks for your response. In the market of HLS tools there are some that can support mixed software/hardware co-simulation. These, however, are not as good or efficient as Vivado in translating C code to HDL. But since it is possible to import your own HDL functions into these tools I am wondering whether Vivado-generated HDL can be imported to them. Or is Vivado-generated code completely proprietary? It should be noted that these tools can be configured to use Xilinx ISE for synthesis and that the target FPGA chips will be Xilinx ones. Sorry for making reference to rival products in your forum but if Vivado cannot offer entirely what we want we need to think about combining it with other tools.

 

Thanks in advance,

Jason




Cheers,
Jim
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jasonjohnson196
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Registered: ‎04-17-2013

I guess that you imply using Zync’s ARM processor as the “host PC” and Zync’s custom FPGA fabric, well, as “the FPGA chip coprocessor”. It sounds a good idea given that on Zynq the ARM CPU speed is 866MHZ (or even 1GHz) and the communication between the ARM CPU and the FPGA should be faster as it will be on the same chip.

 

But still the problem is that you cannot “see” the simulation (configure input parameters or data inputs or display output results). Of course you can run RT Linux on the ARM processor, but in this case don’t you still need some kind of software driver coding and interface set up in order to achieve a SW/HW co-simulation? Also I am wondering what is the sustained data rate between the ARM CPU and the FPGA inside Zynq since AXI interconnects are used. Is it equal to the speed of transceivers? i.e. 6.5 Gb/s or 12.5Gb/s (depending on the speed grade)?

 

Anyway even if with the above approach a sw/hw co-simulation is feasible there is still the problem of the number of FPGA resources required for our algorithm. The maximum amount of logic cells available in a Zynq chip is 444k logic cells (in Z-7100). And Z-7100 is not currently available in any of-the-shelf development board. There is of course one with Z-7045 which contains 350K logic cells. Anyway in case of limited resources the alternative to using  a Zynq chip is to use a larger FPGA and synthesise a soft microprocessor (nb we can get access to ARM IP soft cores) and do a similar job as with Zynq. But in this case the problem is that the CPU clock frequency will be too low.  

 

It seems that severe compromises must be made in one way or the other. 

 

Regards,

Jason

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herver
Xilinx Employee
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Registered: ‎08-17-2011

Hello Jason,

 

Okay, it looks like the previous posts didn't help you.

 

I'm not familiar with FPGA HW cosimulation, which is basically having an FPGA being used as HW accelerator for a simulator running on a PC.

 

I'm assuming that you have a flow that you are using to do HW cosimulation.

 

Correct me if I'm wrong but I assume the flow is something along those lines: after starting ISIM, some bitstream would be loaded in the FPGA then some input data would be transferred to the FPGA for processing, generating partial output data in the FPGA which would be returned to the host PC. In a final step, said partial output data may potentially be futher processed in the simulator.

 

 

Now this is my question: I'm not sure that I understand what makes you think that the RTL generated by VHLS can't be used in in the above flow. AFAIK the RTL generated is "generic" RTL and should be usable in any flow.

-> Could you clarify?

 

 

Please note as well, that the advantage of using VHLS would be to do your code / IP simulations from C and verified within the tool, via C and RTL cosimulation, so that doing extensive RTL simulation would not be necessary.

I appreciate this is needed (for various reasons) but again the advantage here is that you would need to do less of them.

The ultimate goal of VHLS is to provide an IP that can be integrated into a larger FPGA system and be run; this is what my colleagues pointed you towards; it doesn't stop at the HW cosimulation level.

 

 

I hope this helps.

 

- Hervé

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jasonjohnson196
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Hi Hervé,

 

Let me clarify. Our goal is to perform hardware co-simulation for ACCELERATING THE EXECUTION OF SCIENTIFIC ALGORITHMS THAT ARE CURRENTLY WRITTEN IN C. The whole program will run on a PC and the computationally intensive tasks offloaded to the FPGA for co-processing. Ideally we want to interface a software portion written in C (in Visual Studio or any other IDE) with hardware processes running on an FPGA chip (or chips). Much like CUDA C and Nvidia drivers do with GPUs (as I mentioned in my very first post).

 

Theoretically something equivalent can be fulfilled by using Xilinx System Generator and performing a gigabit Ethernet co-simulation with some processes running on the FPGA chip and some in Simulink. But this approach is far from ideal as there is a lot of latency in the communication resulting to most of the speedup achieved by parallel processing (in the FPGA chip) to be lost. For this reason we want to use DMA transfers through a PCI express gen 3 interconnection.

 

We know that the code generated by Vivado is generic and can be included in a co-simulation flow. That’s why it can be wrapped up (automatically) and included in Xilinx System Generator (XSG). But unfortunately XSG cannot create interfaces for a PCI express communication.

 

So we need alternative tools or create this interface manually by ourselves. In the latter case we will need to wrap up the module(s) created by Vivado, create an interface inside the FPGA (buffers, controllers etc complying with the PCI express protocol etc), potentially code some kind of firmware and also create an interface in the PC side (i.e. software API and link it with the board drivers). This MANUAL creation of the software/hardware interface (to enable the PC to talk to the FPGA via PCI express DMAs) is what we want to avoid.  So we were wondering whether Vivado or any other Xilinx tool could offer this automatic interface generation (both in the software and hardware side) and perform co-simualtion for the platforms we want.

 

Now isim can support hardware co-simulation. But for purposes of verifying the HDL design. Not for accelerating algorithms (unless I suppose you write them entirely -i.e. the software portion as well- in VHDL or Verilog).

 

Regards,

 

Jason

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