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sharyumukhekar
Observer
Observer
742 Views
Registered: ‎07-01-2018

Drastic increment is clock period after addition of 2 lines

We are designing a architecture in which msg is received and delivered to output queue. Along with these msg statistics are mentained about count of successfully or errored received msg and count of successfully or errored delived msg. When the code is in state where delivered count code is not added then following is the performance matrix.

+ Timing (ns):
* Summary:
+--------+-------+----------+------------+
| Clock | Target| Estimated| Uncertainty|
+--------+-------+----------+------------+
|ap_clk | 2.00| 2.935| 0.25|
+--------+-------+----------+------------+

+ Latency (clock cycles):
* Summary:
+-----+-----+-----+-----+----------+
| Latency | Interval | Pipeline |
| min | max | min | max | Type |
+-----+-----+-----+-----+----------+
| 5| 5| 2| 2| function |
+-----+-----+-----+-----+----------+

 

After adding the cnt code as below:

if( message.error == 1 ) {

     dlv_stat[ Channel_ID ].err = err + 1;

 } else {

    dlv_stat[ Channel_ID ].succ = succ + 1;

}

Where err and succ veriables are initiated with dlv_stat[ Channel_ID ].err/succ initially

Updated stats are below:

+ Timing (ns):
* Summary:
+--------+-------+----------+------------+
| Clock | Target| Estimated| Uncertainty|
+--------+-------+----------+------------+
|ap_clk | 2.00| 5.560| 0.25|
+--------+-------+----------+------------+

+ Latency (clock cycles):
* Summary:
+-----+-----+-----+-----+----------+
| Latency | Interval | Pipeline |
| min | max | min | max | Type |
+-----+-----+-----+-----+----------+
| 3| 3| 2| 2| function |
+-----+-----+-----+-----+----------+

 

Estimated timing are increased drastically.

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1 Reply
julian.spahr
Participant
Participant
704 Views
Registered: ‎06-28-2018

Hi sharyumukhekar,

It is difficult to determine the exact reason for this, as we have only seen that short snippet of the code.

I would suggest using the HLS Analysis tool to find what path is causing this. Also, during synthesis, you'll see the results of the synthesis in blue letters in the console window. You should be able to find the critical path this way.

Also, if your target is to reach 3 ns of CLK period, I suggest telling the HLS tool to synthesize for a less restrictive clock (maybe 4 ns instead of 2). For me, at times, the tool was able to generate a better timing with a less restrictive clock, than with a very restrictive one. Maybe you'll lucky and HLS calculates a 3.5 ns estimated CLK when the Target is 4 or 5?

Cheers,

Julian

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