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Registered: ‎06-18-2019

[Error: v++ 203-711] Vitis HLS about Multi-Core Processing

Hello all,

I tried to implement multi-core process module using Vitis HLS.

I want to find out whether it can be implemented or not so the following is the very simple code to test it out.

-------------------------------------------------------------------------------------------------------------------------

void readquery(float* query, float* querydata1, float* querydata2, int iteration) {
 memcpy(querydata1, query+(iteration+0)*VECDIM, VECDIM*4);
 memcpy(querydata2, query+(iteration+1)*VECDIM, VECDIM*4);
}

void distance(float* querydata1, float* querydata2, float*outbuffer1, int iteration) {
  //Simple code for caculating distance btw two query data

}

void processor1(float* query, float* outbuffer1, int iteration) {
  float querydata1[VECDIM];
  float querydata2[VECDIM];
  readquery(query, querydata1, querydata2, iteration);
  distance(querydata1, querydata2, outbuffer1, iteration);
}

void processor2(float* query, float* outbuffer1, int iteration) {
  float querydata1[VECDIM];
  float querydata2[VECDIM];
  readquery(query, querydata1, querydata2, iteration);
  distance(querydata1, querydata2, outbuffer1, iteration);
}

void krnl_multiprocess(float* query, float* out) {
  #pragma HLS INTERFACE m_axi port = query offset = slave bundle = gmem
  #pragma HLS INTERFACE m_axi port = out offset = slave bundle = gmem

  #pragma HLS INTERFACE s_axilite port = query bundle = control
  #pragma HLS INTERFACE s_axilite port = out bundle = control
  #pragma HLS INTERFACE s_axilite port = return bundle = control

  int iteration = 0;

  float outbuffer1[4];
  float outbuffer2[4];

  for(iteration = 0; iteration < 4; iteration=iteration+2) {
  #pragma HLS dataflow
  #pragma HLS stable variable=query
  processor1(query, outbuffer1, iteration);
  processor2(query, outbuffer2, iteration+1);
  }
}

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First, when i remove the #pragma it is possible to synthesize but when i check the overall operating time, it seems that the processor1 and processor2 work sequentially.

So when i add the #pragma for task pipeline, the following error message is occurred.

ERROR: [v++ 203-711] Bundled bus interface gmem failed dataflow checking: it cannot read data in multiple processes. This is allowed only if the shared array is marked as stable. Consult the user guide on usage of the stable HLS pragma/directive.
ERROR: [v++ 203-711] Bundled bus interface gmem has read operations in function: 'processor1' and 'processor2'.
ERROR: [v++ 203-711] Bundled bus interface query failed dataflow checking: it cannot read data in multiple processes. This is allowed only if the shared array is marked as stable. Consult the user guide on usage of the stable HLS pragma/directive.
ERROR: [v++ 203-711] Bundled bus interface query has read operations in function: 'processor1' and 'processor2'.
ERROR: [v++ 200-70] Pre-synthesis failed.

I want to implement the overall system that two processor with shared global memory and the two processor is fully independent so it can run parallelly.

How to modify the code to implement my system?

 

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