Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎02-23-2021

FPGA output differs from Vivado HLS C/RTL simulation


I have designed an IP with Vivado HLS. I verified correct output of the C code using the C simulator, and the cosim RTL simulation also shows the same output. 

When I run this design on the FPGA and inspect the inputs and outputs using the ILA, the output of the IP is different. It's not like there is total garbage coming out, because the results are somewhat similar and follow the same pattern. The output are fixed point numbers (16 bit width, 8 bits fractional). 

The IP accepts a sequence of inputs and processes these inputs before a sequence of outputs is produced. Of course I feed the input with the same values as in the C/cosim simulation. The inputs are all constant values, to make sure that I don't have to synchronize the start of a new sequence. 

I tried changing the reset from control to state, but this does not seem to have any influence. 

Can anybody point me in the right direction? Thank you


0 Kudos
2 Replies
Registered: ‎07-09-2009

Easy questions first ,

do you have correct / full timing constraints in place /

   does the design pass timing when you synthesise ?

do you have any data crossing clock domains ? how have you accounted for that ?

Do you have any significant warnings in the vivado output ?

The ILA, 

   is it running at the same clock as the data your looking at ?

      is data only clocked in to the ILA when the data is valid ?

why is your Tready toggling in one example , not the other ?


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Registered: ‎02-23-2021

Thanks for replying drjohnsmith,

I have checked the timing constraints and after the implementation phase all timing constraints are met. I have also checked the timing after the design is synthesized, and here the Total Hold Slack (THS) is really bad over -900ns. I don't know if this is a problem, since after the implementation phase the THS is 0ns.

Both ILA and the IP (and everything else in the FPGA) are running on the same clock (100MHz), so there are no multiple clock domains.

I don't see any alarming warnings (there are no errors of course). 

The ILA clocks in data after I trigger the ILA, so I also see the outputs of the IP when the output is not valid. 

I am not sure why the Tready signal is toggling in the cosim simulation and not in the FPGA ILA. The Vivado HLS is of the ap_ctrl_none type.

0 Kudos