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raymond715
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Registered: ‎10-12-2019

[HLS] 1 bit if condition error

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Hi, 

I try to implement a low cost shift function, which include 2's complement operation. When I do complement operation, C simulation result is just what I want and on-board result is 2's complement represent of C simulation, for example if C simulation is "0xf200, 0x480, 0xf900, ...", then on-board result is "0x0e00, 0xfb80, 0x700". Code is shown below. Fig 1 is C++ code and Fig 2 is verilog  code generated by HLS. Variable `in_sign` in Fig 1 represent sign. `in_sign == 1` is negative and 2's complement is need. `in_sign == 0` represent positive. I think there is something wrong about if condition but I cannot find it. Thanks for your time and looking forward to any suggestion.

Fig 1:

3.png

 

Fig 2:

2.png

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avcon_lee
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Registered: ‎07-17-2014

@raymond715 

In fact, you can directly put the RTL code generated by HLS into your project, and then use chipscope to see what is the value of tmp_V_fu_30_p3, and what caused it?

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calibra
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What  is wrong ?

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raymond715
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Registered: ‎10-12-2019

Hi, calibra 

Thanks for your reply.

The problem is result of C simulation is what I want, but when I place my code on board, what I get is the 2's complement represent of C simulation. For example, if C simulation output is "0xf200, 0x480, 0xf900, ...", wtih same input, on-board result is "0x0e00, 0xfb80, 0x700", which is not what I want. C simulation should be same as on-board result. I think there is something wrong about if condition. Because if I remove if/else in Fig 1 and test each branch of if/else, C simulation result and on-board result is both correct. So, I guess that when if condition in C simulation return 1, correspond verilog if condition return 0 and that is why I get different result from C simulation and on-board test. However, I cannot find any problem in my C code or verilog code generate by HLS.

I don't know if I have expressed myself clearly. Anyway, thanks for your time and looking forward to your reply.

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avcon_lee
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@raymond715 

Figure 1 shows the C code of HLS. What is the original C code like?

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raymond715
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Registered: ‎10-12-2019

Hi, avcon_lee 

What do you mean original C code? Is following figure what you want?

4.png

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avcon_lee
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@raymond715 

What are the input data for in_x and in_shift in simulation?

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raymond715
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Registered: ‎10-12-2019

Hi, avcon_lee 

in_x: 0xe4 0x09 0xf2. in_shift: 0x2.

Current code only calculate 2's complement. Shift have been annotated. 

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avcon_lee
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@raymond715 

It's really strange. Is the data in the actual project the same. Has RTL been simulated.

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raymond715
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Hi, avcon_lee 

Data is same. I have caught the signal of input port with ILA. RTL is not simulated. I develop with HLS and just check verilog to help me locate bug. It is strange if verilog code is correct. Is it possible a bug of HLS or vivado? May be I should implement my function in another way. Anyway, really thanks for your help ^_^.

 

Best regards

Raymond

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avcon_lee
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Registered: ‎07-17-2014

@raymond715 

In fact, you can directly put the RTL code generated by HLS into your project, and then use chipscope to see what is the value of tmp_V_fu_30_p3, and what caused it?

View solution in original post

raymond715
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Registered: ‎10-12-2019

Hi, avcon_lee 

Really thanks for your help! Finally, I found that my shift function is correct. Wrong output is caused by other part of my project, which I haven't found yet. I apply shift function in another project and finally get what I want. Sorry to bother you with such stupid question and thanks again for your time.

Best regards

Raymond

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