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Observer fabios89
Observer
3,863 Views
Registered: ‎04-12-2016

HLS Analysis perspective - bit-width

hello guys,

in analysis perspective when I select an item or an instance some information are shown in the properties panel. I am interested to understand what refers precisely the bit-width entry.

 

thank you.

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5 Replies
Moderator
Moderator
3,853 Views
Registered: ‎07-01-2015

Re: HLS Analysis perspective - bit-width

Hi @fabios89,

 

Please go through page-45 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug902-vivado-high-level-synthesis.pdf

 

Can you please share a snapshot of the info you are looking for?

Thanks,
Arpan
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Observer fabios89
Observer
3,846 Views
Registered: ‎04-12-2016

Re: HLS Analysis perspective - bit-width

thanks @arpansur 

I had already read the file that you indicated to me but I have not found what I needed.
here is the snapshot.

 

I am interested to know what indicates bit_width = 40

 

 

Thanks,
Fabio

Schermata del 2016-12-15 15:20:36.png
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Moderator
Moderator
3,793 Views
Registered: ‎07-01-2015

Re: HLS Analysis perspective - bit-width

Hi @fabios89,

 

Can you please verify it it has RTL name in properties?

If so then you can find the same name in the RTL file generated with declaration std_logic_vector(39 downto 0)

Thanks,
Arpan
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Observer fabios89
Observer
3,787 Views
Registered: ‎04-12-2016

Re: HLS Analysis perspective - bit-width

Thanks for your time @arpansur,

I found the RTL name but in vhdl files I find only std_logic_vector (in0_WIDTH-1 downto 0); where in0_WIDTH is in0_WIDTH: INTEGER: = 32

could you help me to understand? I'm confused I do not know if the bit-widht of property refers to the input data or (in this case) to the division result

 

thank you so much

Fabio

 

the following is the VHDL file for fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u

-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
done : out STD_LOGIC;
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));

function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;

end entity;

architecture rtl of fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);

signal dividend0 : UNSIGNED(in0_WIDTH-1 downto 0);
signal divisor0 : UNSIGNED(in1_WIDTH-1 downto 0);
signal sign0 : UNSIGNED(1 downto 0);
signal dividend_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal remd_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal dividend_tmp_mux : UNSIGNED(in0_WIDTH-1 downto 0);
signal remd_tmp_mux : UNSIGNED(in0_WIDTH-1 downto 0);
signal comb_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal cal_tmp : UNSIGNED(cal_WIDTH downto 0);
signal r_stage : UNSIGNED(in0_WIDTH downto 0);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp, out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp, out_WIDTH));
sign_o <= STD_LOGIC_VECTOR(sign0);

tran0_proc : process (clk)
begin
if (clk'event and clk='1') then
if (start = '1') then
dividend0 <= UNSIGNED(dividend);
divisor0 <= UNSIGNED(divisor);
sign0 <= UNSIGNED(sign_i);
end if;
end if;
end process;

-- r_stage(0)=1:accept input; r_stage(in0_WIDTH)=1:done
done <= r_stage(in0_WIDTH);
one_hot : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
r_stage <= (others => '0');
elsif (ce = '1') then
r_stage <= r_stage(in0_WIDTH-1 downto 0) & start;
end if;
end if;
end process;

-- MUXs
dividend_tmp_mux <= dividend_tmp when (r_stage(0) = '0') else
dividend0;
remd_tmp_mux <= remd_tmp when (r_stage(0) = '0') else
(others => '0');

comb_tmp <= remd_tmp_mux(in0_WIDTH-2 downto 0) & dividend_tmp_mux(in0_WIDTH-1);
cal_tmp <= ('0' & comb_tmp) - ('0' & divisor0);

process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp <= dividend_tmp_mux(in0_WIDTH-2 downto 0) & (not cal_tmp(cal_WIDTH));
if cal_tmp(cal_WIDTH) = '1' then
remd_tmp <= comb_tmp;
else
remd_tmp <= cal_tmp(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;

end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;

architecture rtl of fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div is
component fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;

signal start0 : STD_LOGIC;
signal done0 : STD_LOGIC;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal sign_i : STD_LOGIC_VECTOR(1 downto 0);
signal sign_o : STD_LOGIC_VECTOR(1 downto 0);
begin
fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u_0 : fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
start => start0,
done => done0,
dividend => dividend_u,
divisor => divisor_u,
sign_i => sign_i,
sign_o => sign_o,
quot => quot_u,
remd => remd_u);

sign_i <= (dividend0(in0_WIDTH-1) xor divisor0(in1_WIDTH-1)) & dividend0(in0_WIDTH-1);
dividend_u <= STD_LOGIC_VECTOR(UNSIGNED(not dividend0) + 1) when dividend0(in0_WIDTH-1) = '1' else dividend0;
divisor_u <= STD_LOGIC_VECTOR(UNSIGNED(not divisor0) + 1) when divisor0(in1_WIDTH-1) = '1' else divisor0;

process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
start0 <= start;
end if;
end if;
end process;

process (clk)
begin
if (clk'event and clk = '1') then
done <= done0;
end if;
end process;

process (clk)
begin
if (clk'event and clk = '1') then
if (done0 = '1') then
if (sign_o(1) = '1') then
quot <= STD_LOGIC_VECTOR(UNSIGNED(not quot_u) + 1);
else
quot <= quot_u;
end if;
end if;
end if;
end process;

process (clk)
begin
if (clk'event and clk = '1') then
if (done0 = '1') then
if (sign_o(0) = '1') then
remd <= STD_LOGIC_VECTOR(UNSIGNED(not remd_u) + 1);
else
remd <= remd_u;
end if;
end if;
end if;
end process;

end architecture;

 

Library IEEE;
use IEEE.std_logic_1164.all;

entity fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
start : IN STD_LOGIC;
done : OUT STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;

architecture arch of fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq is
component fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC;
start : IN STD_LOGIC;
done : OUT STD_LOGIC);
end component;

signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);


begin
fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div_U : component fitness_evaluation_fixed_sdiv_40s_14s_40_44_seq_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset,
start => start,
done => done);

end architecture;

 

Schermata del 2016-12-16 10:54:19.png
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Observer fabios89
Observer
3,707 Views
Registered: ‎04-12-2016

Re: HLS Analysis perspective - bit-width

Up

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