12-17-2017 07:37 AM
This is a general question of using HLS. I have a lot of VHDL experience and want to know if I should learn to use HLS.
I also have a lot of experience of both C and C++.
So my questions are:
What is your experience of using HLS?
When is HLS preferable over VHDL/Verilog?
12-17-2017 02:14 PM
@phifred Same thing with Assembly 8086 and C/C++. Why would you ever want to use C/C++ if you can program more effiiciently in Assembly?
1. Perfomance: you cannot outpace the compiler at this point, at least not in large scale. At this point the gain in overall optimizations throughout the system largely outpaces the drawbacks of translated code. HLS is not as complex as Gcc/Clang but it does optimize very well - usually way better that your average RTL engineer would do themselves. At least better than me.
2. Time-to-market: HLS allows you to quickly ship your product through the door. Many times absolute performance is not required but time-to-market is always king.
3. Correctness: there are plenty of cases where maintaining the logic of C/C++ code is way easier than Verilog/VHDL. Algebra is one example that comes to mind. Using HLS ensures in these cases that you will have to deal with code that is expressed in its algorithm's natural form and usually you have to maintain less code.
4. Frequency flexibility: HLS will pipeline - or not - C/C++ expressions according to your requirements. If later you decide to ramp up the frequency of your system, you can just adjust one parameter in HLS and re-generate.
5. Interfaces: HLS gives you for free all interfaces to AXI - streaming, full, lite. You don't need to know the communication protocols to get going.
6. Human Resources: with HLS you can bring in software people to contribute to the project, which at this point in time is way easier to find than a good professional that can write and debug RTL properly.
7. Vivado: HLS fits in the Vivado subsystem as a glove. You just generate the IP and suck it in your block design. Plug and Play. With Verilog/VHDL you would have to go through a lengthy process to generate the IP - which also involves item (5).
8. Debugging: because you can run your C/C++ code in simulation and compare it with the output of simulated verilog, subsystem testing is a breeze with HLS. You can guarantee for sure that the underlying logic is correct before translating it into RTL. This slashes the number of moving parts you have to deal with while debugging your project.
9. It is "free". Unlike other vendors like Catapult, that can cost up to a quarter of million per seat, HLS comes for free with Vivado. So why not to use it?
These are just from the top of my head. I am sure I can find more if I think more. But perhaps our mighty @austin can chip in with more reasons.
12-17-2017 09:41 PM
12-17-2017 11:24 PM
@hbucher Awesome post!
I can see three real reasons/situations not to use HLS:
(1) When you're doing something that HLS can't deal with properly. While the tool is generally very good (and getting better), in a complex project there's a decent chance it'll choke on something. Finding that can be a challenge, and there's no easy way to fix it other than rewriting the code and hoping that the new layout is more acceptable. This is no different from persuading the Vivado synthesis tool to accept HDL code, and it's improving over time.
(2) When you need to very heavily optimize one specific section. Many C compilers will allow for inline assembly code; but HLS has no "inline HDL" equivalent. However, as was mentioned above, at the larger scale HLS is probably better at doing optimization than you are. As such, this is only useful if you can easily separate that single section of code.
(3) Precise timing. HLS is not built for doing cycle-accurate input/output. If you want to read video from a camera, for example, HLS is not the right tool for the job. It's perfect for the video processing, but the low-level interface should still be HDL.
The last in particular means that you often can't avoid HDL completely. However, the vast majority of "big" FPGA tasks (rather than simple interfacing, as is common for CPLDs) are now becoming very HLS-friendy. With the amount of free IP provided by Xilinx, and hardened IP built into chips (eg. Zynq), true HLS-only designs are becoming increasingly practical.