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Observer dasidler
Registered: ‎04-23-2014

HLS INTERFACE axis naming broken


So i used to use the old directives to generate axi stream interface for my HLS code, for example:

void my_function(stream<ap_uint<16> > &inputXYZ)


#pragma HLS resource core=AXI4Stream variable=inputXYZ metadata="-bus_bundle s_axis_xyz"



The nice thing about this pragma is that i can use an axi style (s_axis_*) name for the external port, and in software a use sth like "inputXYZ", this also as you can imagine this results in the following port:





Now since Vivado 2015.3 or so, this directive is officially deprecated, however i can not get the same result with the new native directive.

Now with the new directive, i have to do the following

void my_function(stream<ap_uint<16> > &s_axis_xyz)


#pragma HLS INTERFACE axis port=s_axis_xyz


First, i have to use the same name in software as gets generated for verilog, i can live with that.

Second, the generated output ports, include weird _V_V, and there is no way to get ride of it, see:




Not only is this completely ugly, but it also means that i have to rename all wires in RTL if i actually want to move from the old directive to the new one.



I only found a way for structs to fix this through the DATA_PACK directive, e.g.:
#pragma HLS DATA_PACK variable=s_axis_xyz instance=s_axis_xyz

Here i can specify explicitly the output name with "instance", i am wondering why this is not the default behavior?


For non-structs, as in my example ap_uint<16>, there is no way to specify the name of the external port when using INTERFACE axis.

How can this be fixed?

What is the reason for this weird behavior?


I tried Vivado 2015.3 and 2016.2.

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Participant jehandad
Registered: ‎06-08-2016

Re: HLS INTERFACE axis naming broken



This is a bug in Vivado and should not be the way it appears. Sadly I raised the same issue and was asked to file a service request. My account approval does not seem to allow that. This is a major pain for me since I am auto generating HLS code and then stitching it in verilog, as you can such a facility would be really convenient.


I am sure that there is some way to predict if there would be two '_V' or one ( I have not seem more than that ). But I dont know how.



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