UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor byke
Visitor
1,038 Views
Registered: ‎04-11-2018

HLS Integrator - fifo interface

Dears,

I would like to connectVivado HLS FIFO port to FIFO Generator wiazard port from Vivaod IP Integrator. When FIFO interface is exported with Vivado HLS it comes with active low empty and full signal. FIFO generator has active high empty and full signals. So, these two interfaces could not be connected directly, without inverters in between. Is there some option in Vivado HLS or IP integrator which will make there two interfaces compatibile? I tried this in Vivado 2017.2 2017.4 2018.1.

Regards.

0 Kudos
2 Replies
Scholar hbucher
Scholar
1,002 Views
Registered: ‎03-22-2016

Re: HLS Integrator - fifo interface

@byke  I guess you are right. There should be at least an option to make ap_fifo signals active high - as with the other signals.

Can you use AXI-stream instead? 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
0 Kudos
Visitor byke
Visitor
985 Views
Registered: ‎04-11-2018

Re: HLS Integrator - fifo interface

@hbucher, I tried to use AXI stream. But the problem is that I have to use SystemC for this model and AXI Lite for configuration. I can not synthetase both AXI Lite and AXI Stream at same time, using SystemC. I post minimal example in topic "SystemC AXI Lite and AXI Stream". There is workaround, I can make Vivado HLS IP with only sc_fifo inside, but I really do not want to do that. I hope, there is more elegant solution for this.

0 Kudos