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gvirbila
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Registered: ‎07-01-2013

HLS SSR FFT

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Does anyone have an example for using the HLS SSR FFT (ug902 v2019.1)?

Gabriel

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fguy
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Registered: ‎06-06-2014
The topic can be closed due to the removal of IP SSR FFT in Vivado & Vitis 2019.2.
The hope remains that the next reincarnation of this IP will be more adequate.

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fguy
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The core sources were available back in 2018.3. The source text contains 4 syntax errors - they are simple and easy to correct, but the very fact of their presence leads to sad thoughts. The core documentation also does not match what it is. The core is collected only for fixed-point numbers, for the float type we have an error in the syntax (not related to the above), and double is not synthesized. The size of the synthesized core for a fixed point is not acceptable for use. It is also synthesized not for operation in pipeline mode.

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wenchen
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Registered: ‎05-27-2018

Hi @fguy @gvirbila 

      In UG902 V2019.1,page 245,It is clearly stated that the recommended starting point is to start with float/double inner type in std::complex<> and verify the SNR against a reference model, such as the Matlab/Python/Octave/Simulink – whichever modeling language or tools are used by generating golden test vectors. The synthesizable version of the SSR FFT currently only supports ap_fixed<> inner type, so the next step is to start experimenting with a fixed point model.

      The FFT cannot be used in a region which is pipelined. If high-performance operation is required, pipeline the loops or functions before and after the FFT then use dataflow optimization on all loops and functions in the region. If you have to use the float tpye, consider the FFT lP Library instead of SSR FFT.

Thanks,

Wen

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fguy
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According to its functionality, the IP SSR FFT should be designed to process "wide" data coming, for example, with IP JESD for ADCs operating at frequencies above the maximum allowable for ordinary IP FFT. For example, with an ADC at a sampling frequency of 3.2 GHz, the output of IP JESD will be 256 bits wide with a frequency of 200 MHz. They could be processed by one IP SSR FFT operating in pipeline mode or by fragmenting data into 3-4 "ordinary" IP FFTs. The first option would be much preferable, but in the current state it cannot be implemented, because the inability of IP SSR FFT to operate in pipeline mode makes its existence useless.

gvirbila
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Registered: ‎07-01-2013

I have made some progress but am having trouble instantiating a SSR FFT module. UG902 v2019.1, pg. 249 states that the FFT should be called as follows:

hls::ssr_fft::fft<ssr_fft_params>(inD,outD);

after I have set the ssr_fft_params based on the extended struct, ssr_fft_default_params. At this point, HLS complains of an invalid overload. I have dug somewhat throught hls_ssr_fft.h file but am still at a loss.

What is the correct instantiation?

 

 

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fguy
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Using IP SSR FFT is similar to using regular IP FFT in HLS. I took the project "Xilinx\Vivado\2019.1\examples\design\FFT\fft_single_x_complex" as the basis.

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gvirbila
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Registered: ‎07-01-2013

Hey fguy,

I have looked at the example you recommened but cannot for the life me make the SSR FFT work. Do you have an example line of code for instantiation and calling of the module?

 

Gabriel

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fguy
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Registered: ‎06-06-2014

I already wrote above that this IP is useless - in the current state it is not applicable for its intended purpose - there is no pipeline and there is no support for data in the float format.

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fguy
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Registered: ‎06-06-2014
The topic can be closed due to the removal of IP SSR FFT in Vivado & Vitis 2019.2.
The hope remains that the next reincarnation of this IP will be more adequate.

View solution in original post

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fguy
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Registered: ‎06-06-2014

OOPS!!!

The IP SSR FFT has moved to the Vitis library and now, according to the documentation and examples, now supports the complex float data type. Is it possible to synthesize the current version using HLS and get an IP for Vivado?

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gvirbila
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Interesting... Can you point me in the right direction? I have not used Vitis before.

Gabriel

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fguy
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Registered: ‎06-06-2014

The source code of this kernel for Vitis, usage examples and documentation links can be found at https://github.com/Xilinx/Vitis_Libraries/tree/master/dsp
The source code for Vitis has much in common with HLS - perhaps they can also be adapted to form regular IPs for Vivado. I would like to hear from Xilinx experts about this.

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baileyji
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Registered: ‎02-20-2019

You might see my post here. That will show the basics for the xilinx example in HLS but I've also found some bugs.

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