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Participant
Participant
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Registered: ‎09-09-2010

HLS and System generator algebraic loop issue on a FIFO

Not having had any response since more than a month, I try the luck in this forum section. Maybe I've posted in the wrong place in the first instance.

In a Nutshell, I'm forced to use fifos to decouple a chain of hls ip cores to perform an image processing pipeline.

Problem arises for algebraic loop errors in system generator, on the rd path to the fifo from the HLS block.

I've tried assert blocks, but with no luck at all. Please refer to this old post of mine for a detailed explanation:

 

https://forums.xilinx.com/t5/DSP-and-Video/HLS-AND-AP-FIFO-IN-SYSTEM-GENERATOR/m-p/814448/highlight/false#M18074

 

thank you in advance for any hints or suggestions. The're hihgly appreciated.

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