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telan_tan
Visitor
Visitor
520 Views
Registered: ‎07-19-2020

HLS generate x state

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A simple  AXI Master -> AXI Stream example was created, after co-simulation I found there were X state for tuser/tlast/tdata signals, so the question is how to get rid of them, thanks.

#include "v_tpg.h"


void v_tpg ( axis& OUTPUT_STREAM,
		   int lines,
		   int cols,
           int pattern,
		   int* image){

#pragma HLS STREAM variable=OUTPUT_STREAM
#pragma HLS INTERFACE m_axi depth=640 port=image offset=slave
#pragma HLS INTERFACE axis register both port=OUTPUT_STREAM

#pragma HLS INTERFACE ap_none port=lines
#pragma HLS INTERFACE ap_none port=cols
#pragma HLS INTERFACE ap_none port=pattern

VIDEO_COMP tpg_gen;
int i = 0;
int y = 0;
int x = 0;
int frm_lines =0;
int frame[MAX_WIDTH];


if(pattern==0) {
 for (y =0; y<lines; y++){
    memcpy(frame,image,cols*sizeof(int));
     for (x =0; x < cols; x++) {
#pragma HLS PIPELINE
        if (y == 0 && x == 0 ){
            tpg_gen.user = 1;
            tpg_gen.data = frame[x];
        }
        else{
            if (x == cols-1 ){
                tpg_gen.last = 1;
                tpg_gen.data = frame[x];
            }
            else{
                tpg_gen.last = 0;
                tpg_gen.user = 0;
                tpg_gen.data = frame[x];
            }
        }
        OUTPUT_STREAM.write(tpg_gen);
    }
  }
}
else if(pattern==1) {
 for (y =0; y<lines; y++){
    memcpy(frame,image,cols*sizeof(int));
     for (x =0; x < cols; x++) {
#pragma HLS PIPELINE
        if (y == 0 && x == 0 ){
            tpg_gen.user = 1;
            tpg_gen.data = y;
        }
        else{
            if (x == cols-1 ){
                tpg_gen.last = 1;
                tpg_gen.data = y;
            }
            else{
                tpg_gen.last = 0;
                tpg_gen.user = 0;
                tpg_gen.data = y;
            }
        }
        OUTPUT_STREAM.write(tpg_gen);
    }
  }
}
else {
 for (y =0; y<lines; y++){
    memcpy(frame,image,cols*sizeof(int));
     for (x =0; x < cols; x++) {
#pragma HLS PIPELINE
        if (y == 0 && x == 0 ){
            tpg_gen.user = 1;
            tpg_gen.data = x;
        }
        else{
            if (x == cols-1 ){
                tpg_gen.last = 1;
                tpg_gen.data = x;
            }
            else{
                tpg_gen.last = 0;
                tpg_gen.user = 0;
                tpg_gen.data = x;
            }
        }
        OUTPUT_STREAM.write(tpg_gen);
    }
  }

}

}

hls.png

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1 Solution

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preusser
Adventurer
Adventurer
488 Views
Registered: ‎05-19-2014
Sorry, I would not know.
While you might have your reasons to dislike the unknown outputs, I would encourage you to reconsider. By specifying those 'X' outputs, Vivado HLS communicates logic optimization potential to the backend RTL synthesis. Again, I do not know why and how it should allow the user to take this opportunity away.

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3 Replies
preusser
Adventurer
Adventurer
511 Views
Registered: ‎05-19-2014
`TVALID` is not asserted. So, there is certainly no protocol violation. HLS is legally allowed to synthesize such behavior.
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telan_tan
Visitor
Visitor
491 Views
Registered: ‎07-19-2020

Yes, there's no protocol violation. I just want to know is there any Directive or Config to remove those X state.

Tags (1)
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preusser
Adventurer
Adventurer
489 Views
Registered: ‎05-19-2014
Sorry, I would not know.
While you might have your reasons to dislike the unknown outputs, I would encourage you to reconsider. By specifying those 'X' outputs, Vivado HLS communicates logic optimization potential to the backend RTL synthesis. Again, I do not know why and how it should allow the user to take this opportunity away.

View solution in original post