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s62665
Visitor
Visitor
2,523 Views
Registered: ‎05-13-2018

HLS generated SystemC Code does not build

Hi,
I try to use the SystemC code generated by HLS during synthse.
I noticed that although HLS generates SystemC code from my C code,
it includes headers in which the AXI buses must be declared but with the bus designations from my C code.
Unfortunately these headers are not generated and I can't find them anywhere.
Does anyone have an idea how I can generate them or where I can find them?

Thanks

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8 Replies
chrisz
Xilinx Employee
Xilinx Employee
2,473 Views
Registered: ‎05-06-2008

Hello @s62665,

 

I am not sure why the SystemC code is not building correct.  Can you PM with your source code, so I can investigate this issue further?

 

Thanks,

Chris

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s62665
Visitor
Visitor
2,431 Views
Registered: ‎05-13-2018

Hi Chris,

I have create a example Code that I can share with you, but have the Same problem:

my C Code is :

#include "myLEDTest.h"

void myLEDTest (char *inputRegister, char *outputToLED)
{
	#pragma HLS INTERFACE s_axilite port=inputRegister bundle=LED_BUS
	#pragma HLS INTERFACE s_axilite port=return bundle=LED_BUS

	*outputToLED = *inputRegister;
}


The Testbench Code is :

#include "myLEDTest.h"
#include "stdio.h"

#define TESTINPUT 4
#define HLS_FALSE 1
#define HLS_TRUE 0

int main(){
	char input=TESTINPUT,output=0;
	int retValue = HLS_FALSE;

	myLEDTest(&input,&output);
	if(output==TESTINPUT)
	{
		retValue = HLS_TRUE;
		printf("\nSuccessfull\n");
	}

	return retValue;
}


The Generated Synthesis SystemC Header is:

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.1
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

#ifndef _myLEDTest_HH_
#define _myLEDTest_HH_

#include "systemc.h"
#include "AESL_pkg.h"

#include "myLEDTest_LED_BUS_s_axi.h"

namespace ap_rtl {

template<unsigned int C_S_AXI_LED_BUS_ADDR_WIDTH = 5,
         unsigned int C_S_AXI_LED_BUS_DATA_WIDTH = 32>
struct myLEDTest : public sc_module {
    // Port declarations 22
    sc_out< sc_lv<8> > outputToLED;
    sc_out< sc_logic > outputToLED_ap_vld;
    sc_in< sc_logic > s_axi_LED_BUS_AWVALID;
    sc_out< sc_logic > s_axi_LED_BUS_AWREADY;
    sc_in< sc_uint<C_S_AXI_LED_BUS_ADDR_WIDTH> > s_axi_LED_BUS_AWADDR;
    sc_in< sc_logic > s_axi_LED_BUS_WVALID;
    sc_out< sc_logic > s_axi_LED_BUS_WREADY;
    sc_in< sc_uint<C_S_AXI_LED_BUS_DATA_WIDTH> > s_axi_LED_BUS_WDATA;
    sc_in< sc_uint<C_S_AXI_LED_BUS_DATA_WIDTH/8> > s_axi_LED_BUS_WSTRB;
    sc_in< sc_logic > s_axi_LED_BUS_ARVALID;
    sc_out< sc_logic > s_axi_LED_BUS_ARREADY;
    sc_in< sc_uint<C_S_AXI_LED_BUS_ADDR_WIDTH> > s_axi_LED_BUS_ARADDR;
    sc_out< sc_logic > s_axi_LED_BUS_RVALID;
    sc_in< sc_logic > s_axi_LED_BUS_RREADY;
    sc_out< sc_uint<C_S_AXI_LED_BUS_DATA_WIDTH> > s_axi_LED_BUS_RDATA;
    sc_out< sc_lv<2> > s_axi_LED_BUS_RRESP;
    sc_out< sc_logic > s_axi_LED_BUS_BVALID;
    sc_in< sc_logic > s_axi_LED_BUS_BREADY;
    sc_out< sc_lv<2> > s_axi_LED_BUS_BRESP;
    sc_in_clk ap_clk;
    sc_in< sc_logic > ap_rst_n;
    sc_out< sc_logic > interrupt;
    sc_signal< sc_logic > ap_var_for_const0;
    // Port declarations for the virtual clock. 
    sc_in_clk ap_virtual_clock;


    // Module declarations
    myLEDTest(sc_module_name name);
    SC_HAS_PROCESS(myLEDTest);

    ~myLEDTest();

    sc_trace_file* mVcdFile;

    ofstream mHdltvinHandle;
    ofstream mHdltvoutHandle;
    myLEDTest_LED_BUS_s_axi<C_S_AXI_LED_BUS_ADDR_WIDTH,C_S_AXI_LED_BUS_DATA_WIDTH>* myLEDTest_LED_BUS_s_axi_U;
    sc_signal< sc_logic > ap_start;
    sc_signal< sc_logic > ap_done;
    sc_signal< sc_logic > ap_idle;
    sc_signal< sc_logic > ap_ready;
    sc_signal< sc_lv<8> > inputRegister;
    sc_signal< sc_logic > ap_rst_n_inv;
    static const sc_logic ap_const_logic_1;
    static const int C_S_AXI_DATA_WIDTH;
    static const sc_logic ap_const_logic_0;
    static const bool ap_const_boolean_1;
    // Thread declarations
    void thread_ap_var_for_const0();
    void thread_ap_done();
    void thread_ap_idle();
    void thread_ap_ready();
    void thread_ap_rst_n_inv();
    void thread_outputToLED();
    void thread_outputToLED_ap_vld();
    void thread_hdltv_gen();
};

}

using namespace ap_rtl;

#endif



Maybe you misunderstand me. I can create a IP-Block with that Code. But I would like to use also the Generated Synthesis SystemC Code and also would like to understand the Code.
My Problem is the Line:

    myLEDTest_LED_BUS_s_axi<C_S_AXI_LED_BUS_ADDR_WIDTH,C_S_AXI_LED_BUS_DATA_WIDTH>* myLEDTest_LED_BUS_s_axi_U;


 Here Xilinx define the AXI-Interface. This should come from this include:

#include "myLEDTest_LED_BUS_s_axi.h"


I can't find this include. Is it possible to find that include or are there any Explanations about the AXI-Interface which is here generated.
Please provide me some Informations about the AXI-Interface and where I can find the generated include.
 

Thanks

 

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peadard
Moderator
Moderator
2,366 Views
Registered: ‎02-07-2008

Hi @s62665, what does "myLEDTest.h" contain?

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s62665
Visitor
Visitor
2,299 Views
Registered: ‎05-13-2018

 Hi,

the Header "myLEDTest.h" contain:

void myLEDTest (char *inputRegister, char *outputToLED);

Thanks

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chrisz
Xilinx Employee
Xilinx Employee
2,152 Views
Registered: ‎05-06-2008

Hello @s62665,

 

Why do we want to use 'Generated Synthesis SystemC Code' from the original C++ code?

 

I am not sure why the 'myLEDTest_LED_BUS_s_axi.h' is listed, but not  in the same directory.  

 

Thanks,
Chris

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yhtroom
Visitor
Visitor
2,071 Views
Registered: ‎05-02-2018

Hello Chris,

 

I'm facing the same problem.

 

HLS takes my C++ code and is supposed to translate that into RTL equivalents in 3 languages, VHDL, Verilog, and SystemC.

 

The VHDL and Verilog subfolders under "syn" contain all of the required modules. However, the SystemC folder does not contain all of the .h SystemC files that are needed (my more complicated sub-modules have their .h files, but some simple sub-modules like muxes are missing).

 

As per your earlier question as to why customers may need to use the SystemC RTL files, the SystemC RTL files are very useful for co-simulating the HLS generated modules with software APIs that will use these hardware modules. In other words, I use the HLS generated Verilog RTL for hardware simulation and then eventually full synthesis, but I would also like to use HLS generated SystemC RTL equivalent files for Transaction-Level simulations with my software.

 

This seems to be an ongoing problem even with Vivado HLS 2018.1, can you please provide some insight as to why HLS might be failing to generate all of the SystemC RTL equivalents.

 

INFO: [SYSC 207-301] Generating SystemC RTL for top_level_hw_module

INFO: [VHDL 208-304] Generating VHDL RTL for top_level_hw_module.
INFO: [VLOG 209-307] Generating Verilog RTL for top_level_hw_module.

 

These info messages go through without any warnings or errors. But exactly as the original poster had described, my top_func.h file has #include "sub_module.h", but then my SystemC build fails because not all of these include statements have their corresponding .h files.

 

Thanks

 

s62665
Visitor
Visitor
2,004 Views
Registered: ‎05-13-2018

Hello Chrisz,

i try to use the SystemC Code in a university research project. Like yhtroom we will make a cosimulation of HLS hardware with software for transaction level modeling. I have try HLS 2017.3, 2017.4 and 2018.1 and the files are missing at all versions.

I will test 2018.2 this week. Is there a chance that in future versions the files are gernerated maybe in HLS 2018.3?

 

Thanks

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s62665
Visitor
Visitor
1,965 Views
Registered: ‎05-13-2018

Update:

I tested Vivado 2018.2 and there is the same problem

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