HLS kernel cannot read data from RTL kernel via Stream
I do not find similar questions so I post a new one. RTL kernel is connected with global memory and is responsible to read/write data. Data transfer between RTL kernel and HLS kernel is realized via stream. My problem is that HLS kernel cannot read data from stream. The bitstream is generated successfully and there is no error.
1. Block design: sequential reading/writing, transferring data between two kernels via stream
2. ILA Waveform:
RTL kernel can read data correctly. RTL kernel data_output stream issues one valid signal and does not receive ready signal from HLS kernel. RTL kernel data_input stream does not receive valid signal and always sets ready signal high.
It seems that HLS kernel does not launch properly.
The RTL output data in the bus start from 0, each time increase by 1.
The HLS kernel read the input, add 1 and write the output back to stream.
RTL write data back to global memory.
3. The sequence of enqueueing kernels in host is shown below: