cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
396 Views
Registered: ‎01-15-2020

HLS state machine error trapping

I've written a parser in HLS that is basically a complex state machine. (extract of code below)

I've included some error trapping that should force the state machine to satae SEND_1 whenever (rts & prev_eop) occurs. This does not happen, as proven both in sim,u;ation and in implemented logic.

 

prev_eop should just be the value of eop on the previous function call, but I've also tried just using eop, which is a primary input. No difference.

Code:

void    hls_parse_packet_64

(

    bool            reset,                  // Active high synchronous reset

    bool            rts,                    // Data is available

    bool            *rtr,                   // Data can be accepted

    ap_uint<64>     inword,                 // Current input data word

    bool            sop,                    // Start of packet

    bool            eop,                    // End of packet

 

    ap_uint<128>    *hdr_fifo,              // Data to be written to "header info" FIFO

    bool            *hdr_sop,               // Start-of-packet to the header FIFO

    bool            *hdr_eop,               // End-of-packet to the header FIFO

    bool            hdr_fifo_full           // "header info" FIFO is full

)

{

static     bool            prev_eop;               // Value of EOP on last clock

    // Parse the packet

    if (reset)

        state       =   WAIT_FOR_SOP;

    else if (rts & prev_eop)            // Unconditionally go to state SEND_1 after EOP as an error trap

    {                                   // this is OK because we force rtr low when eop occurs

        state       =   SEND_1;

    }

    else

    {

        switch(state)

        {

            case  WAIT_FOR_SOP:                     // 0x00 - wait for start of packet

                rtr_pre     =   !hdr_fifo_full;

        …

        …

        …

        break;

        }   // end switch(state)

 

 

        *rtr    =   rtr_pre & !(prev_eop & rts);

 

        prev_eop    =   eop & rts;

 

 

    }   // end if(reset)

 

What do I need to do to fix this?

 

 

 

0 Kudos
1 Reply
Highlighted
Moderator
Moderator
302 Views
Registered: ‎05-27-2018

Hi steve.kemplin@commscope.com 

    All the state machine running status can be checked if you have written a c-test bench and debug step by step. 

    Check the value of rts and prev_eop when running the debugger. 

Wen

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos