Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎01-05-2012

How do I troubleshoot when HLS C Synthesis aborts (fails silently)?

I'm currently running Vivado HLS 2017.3, but I've seen the same problem in earlier versions.


Sometimes C Synthesis aborts for a project that works fine in C Simulation, and there are no error messages. Here's an example of the last few lines of output from C Synthesis:

INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:31 ; elapsed = 00:02:30 . Memory (MB): peak = 827.156 ; gain = 771.699
Finished C synthesis.

There should be a whole bunch of other lines between those two, such as "Finished Architecture Synthesis", "Starting hardware synthesis", "Generating SystemC RTL", "Generating VHDL RTL", "Generating Verilog RTL" and "Total elapsed time".


When the problem happens I get none of those messages, and no synthesis report is generated.


Without any error messages, it is impossible to say why synthesis failed. I wind up backing out my changes, then implementing them in baby steps, re-running C Synthesis for each baby step. The first time synthesis aborts I look at the most recent baby step, and try to determine what C Synthesis didn't like about it. This is a long and agonizing process that would be avoided if I could get an error message indicating which code (or at least which source file) was at fault.


Is there some way to get more verbose output when synthesizing, to indicate what failed?


Any other suggestions on troubleshooting this problem?



0 Kudos
0 Replies