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Explorer
Explorer
1,443 Views
Registered: ‎02-08-2018

How to export a design from Vivado HLS to the FPGA board, and use in a host C++ program

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I have written a design in C that is supposed to receive an image array (format uint8_t*) from a host C++ program, convert it from RGB to gray, and then send a new image array back to the host C++ program.  I have successfully synthesized the design in Vivado HLS and exported the RTL design to a .dcp file.  Now I want to know the steps of how to import this design into Vivado, program the FPGA and then compile a host C++ program that can send and receive image data to/from the FPGA after it has been programmed.

 

Thanks,

  ~Alycia

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Xilinx Employee
Xilinx Employee
1,526 Views
Registered: ‎05-06-2008

Hello Agailey,

 

I recommend going through the Vivado HLS Tutorial - UG871 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug871-vivado-high-level-synthesis-tutorial.pdf), chapter 10.  This will give you some insights on the flow you are describing.

 

Good Luck,
Chris

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Xilinx Employee
Xilinx Employee
1,527 Views
Registered: ‎05-06-2008

Hello Agailey,

 

I recommend going through the Vivado HLS Tutorial - UG871 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug871-vivado-high-level-synthesis-tutorial.pdf), chapter 10.  This will give you some insights on the flow you are describing.

 

Good Luck,
Chris

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