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Explorer
Explorer
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Registered: ‎11-21-2013

How to realize function if (!ap_fifo_FIFO.empty) memcpy(ap_fifo_FIFO, *data, NUMOFBYTES);

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Hi, Dear all,

 

I want  a function that if the FIFO is not full, then move data from DDR to ap_fifo interface.

And another function that if the FIFO is not empty, then read data from ap_fifo interface to DDR. Through AXIM4 interface.

...

struct newTask_t {
        uint32_t newTask_info[NUMOFBYTES];
        uint_t newTask_write;
        uint_t newTask_full;
};

struct readyTask_t {
        uint32_t readyTask_info[NUMOFBYTES];
        uint_t readyTask_read;
        uint_t readyTask_empty;
};

...

#pragma HLS INTERFACE ap_fifo port=readyTask
#pragma HLS INTERFACE ap_fifo port=newTask
#pragma HLS INTERFACE m_axi depth=768 port=data bundle=data
...
//a
if(!newTask_full){
 memcpy(newTask, data , NUMOFBYTES);
}

//b
if(!readyTask_empty){
memcpy(data + offset, readyTask, NUMOFBYTES);
}

 

I couldn't find any example making use of empty and full signals of the ap_fifos, could anyone give me a workable example?

 

Thanks!

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Explorer
Explorer
16,478 Views
Registered: ‎11-21-2013

We end up with adding a ap_int<1> interface on the top level function, and connect the fifo.empty/fifo.full signals to this interface in the block design

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Moderator
Moderator
9,661 Views
Registered: ‎04-17-2011

Hello @xubintan
In your case, you have set ap_fifo as a Top-Level Interface, which means that the FIFO you are going to connect is outside HLS IP. In that case, the empty and full signals will be received from the FIFO outside HLS and not internally. This is taken care by the ap_fifo interface as described in Figure 4-10 in the UG: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug902-vivado-high-level-synthesis.pdf (Page-499)

In your case, if you want an internal FIFO and a control logic, you can create an internal stream type:

hls::stream<int> temp;

and use non-blocking statements as below

if(!temp.empty());
//do something;

if(!temp.full());
//do something;

The details of hls::stream can be found in Page-219 onward.

Regards,
Debraj
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Explorer
Explorer
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Registered: ‎11-21-2013

Hi, thank you for your answer.

 

The Non-Blocking Read  in  the "hls_stream.h" file, I've found this:

    bool full() const { return false; }
 
 
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Teacher
Teacher
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Registered: ‎03-31-2012
It is possible that, that's only for C sim and generated hardware behaves differently. One can't fully duplicate RTL testbench behavior in C sim.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Highlighted
Explorer
Explorer
16,479 Views
Registered: ‎11-21-2013

We end up with adding a ap_int<1> interface on the top level function, and connect the fifo.empty/fifo.full signals to this interface in the block design

View solution in original post

0 Kudos